stm32_hal_legacy.h 231 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32_hal_legacy.h
  4. * @author MCD Application Team
  5. * @brief This file contains aliases definition for the STM32Cube HAL constants
  6. * macros and functions maintained for legacy purpose.
  7. ******************************************************************************
  8. * @attention
  9. *
  10. * Copyright (c) 2021 STMicroelectronics.
  11. * All rights reserved.
  12. *
  13. * This software is licensed under terms that can be found in the LICENSE file
  14. * in the root directory of this software component.
  15. * If no LICENSE file comes with this software, it is provided AS-IS.
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32_HAL_LEGACY
  21. #define STM32_HAL_LEGACY
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. /* Exported types ------------------------------------------------------------*/
  27. /* Exported constants --------------------------------------------------------*/
  28. /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
  29. * @{
  30. */
  31. #define AES_FLAG_RDERR CRYP_FLAG_RDERR
  32. #define AES_FLAG_WRERR CRYP_FLAG_WRERR
  33. #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
  34. #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
  35. #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
  36. #if defined(STM32H7) || defined(STM32MP1)
  37. #define CRYP_DATATYPE_32B CRYP_NO_SWAP
  38. #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
  39. #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
  40. #define CRYP_DATATYPE_1B CRYP_BIT_SWAP
  41. #endif /* STM32H7 || STM32MP1 */
  42. /**
  43. * @}
  44. */
  45. /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
  46. * @{
  47. */
  48. #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
  49. #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
  50. #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
  51. #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
  52. #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
  53. #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
  54. #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
  55. #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
  56. #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
  57. #define REGULAR_GROUP ADC_REGULAR_GROUP
  58. #define INJECTED_GROUP ADC_INJECTED_GROUP
  59. #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
  60. #define AWD_EVENT ADC_AWD_EVENT
  61. #define AWD1_EVENT ADC_AWD1_EVENT
  62. #define AWD2_EVENT ADC_AWD2_EVENT
  63. #define AWD3_EVENT ADC_AWD3_EVENT
  64. #define OVR_EVENT ADC_OVR_EVENT
  65. #define JQOVF_EVENT ADC_JQOVF_EVENT
  66. #define ALL_CHANNELS ADC_ALL_CHANNELS
  67. #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
  68. #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
  69. #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
  70. #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
  71. #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
  72. #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
  73. #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
  74. #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
  75. #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
  76. #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
  77. #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
  78. #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
  79. #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
  80. #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
  81. #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
  82. #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
  83. #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
  84. #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
  85. #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
  86. #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
  87. #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
  88. #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
  89. #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
  90. #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
  91. #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
  92. #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
  93. #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
  94. #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
  95. #if defined(STM32H7)
  96. #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
  97. #endif /* STM32H7 */
  98. #if defined(STM32U5)
  99. #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
  100. #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
  101. #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
  102. #endif /* STM32U5 */
  103. #if defined(STM32H5)
  104. #define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
  105. #endif /* STM32H5 */
  106. /**
  107. * @}
  108. */
  109. /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
  110. * @{
  111. */
  112. #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
  113. /**
  114. * @}
  115. */
  116. /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
  117. * @{
  118. */
  119. #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
  120. #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
  121. #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
  122. #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
  123. #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
  124. #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
  125. #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
  126. #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
  127. #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
  128. #if defined(STM32L0)
  129. #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
  130. input 1 for COMP1, LPTIM input 2 for COMP2 */
  131. #endif
  132. #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
  133. #if defined(STM32F373xC) || defined(STM32F378xx)
  134. #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
  135. #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
  136. #endif /* STM32F373xC || STM32F378xx */
  137. #if defined(STM32L0) || defined(STM32L4)
  138. #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
  139. #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
  140. #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
  141. #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
  142. #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
  143. #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
  144. #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
  145. #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
  146. #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
  147. #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
  148. #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
  149. #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
  150. #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
  151. #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
  152. #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
  153. #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
  154. #if defined(STM32L0)
  155. /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
  156. /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
  157. /* to the second dedicated IO (only for COMP2). */
  158. #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
  159. #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
  160. #else
  161. #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
  162. #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
  163. #endif
  164. #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
  165. #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
  166. #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
  167. #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
  168. /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
  169. /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
  170. #if defined(COMP_CSR_LOCK)
  171. #define COMP_FLAG_LOCK COMP_CSR_LOCK
  172. #elif defined(COMP_CSR_COMP1LOCK)
  173. #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
  174. #elif defined(COMP_CSR_COMPxLOCK)
  175. #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
  176. #endif
  177. #if defined(STM32L4)
  178. #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
  179. #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
  180. #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
  181. #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
  182. #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
  183. #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
  184. #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
  185. #endif
  186. #if defined(STM32L0)
  187. #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
  188. #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
  189. #else
  190. #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
  191. #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
  192. #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
  193. #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
  194. #endif
  195. #endif
  196. #if defined(STM32U5)
  197. #define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
  198. #endif
  199. /**
  200. * @}
  201. */
  202. /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
  203. * @{
  204. */
  205. #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
  206. #if defined(STM32U5)
  207. #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
  208. #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
  209. #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
  210. #endif /* STM32U5 */
  211. /**
  212. * @}
  213. */
  214. /** @defgroup CRC_Aliases CRC API aliases
  215. * @{
  216. */
  217. #if defined(STM32H5) || defined(STM32C0)
  218. #else
  219. #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
  220. inter STM32 series compatibility */
  221. #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
  222. inter STM32 series compatibility */
  223. #endif
  224. /**
  225. * @}
  226. */
  227. /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
  228. * @{
  229. */
  230. #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
  231. #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
  232. /**
  233. * @}
  234. */
  235. /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
  236. * @{
  237. */
  238. #define DAC1_CHANNEL_1 DAC_CHANNEL_1
  239. #define DAC1_CHANNEL_2 DAC_CHANNEL_2
  240. #define DAC2_CHANNEL_1 DAC_CHANNEL_1
  241. #define DAC_WAVE_NONE 0x00000000U
  242. #define DAC_WAVE_NOISE DAC_CR_WAVE1_0
  243. #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
  244. #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
  245. #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
  246. #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
  247. #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
  248. #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
  249. #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
  250. #endif
  251. #if defined(STM32U5)
  252. #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
  253. #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
  254. #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
  255. #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
  256. #endif
  257. #if defined(STM32H5)
  258. #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
  259. #define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
  260. #endif
  261. #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
  262. defined(STM32F4) || defined(STM32G4)
  263. #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
  264. #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
  265. #endif
  266. /**
  267. * @}
  268. */
  269. /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
  270. * @{
  271. */
  272. #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
  273. #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
  274. #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
  275. #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
  276. #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
  277. #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
  278. #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
  279. #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
  280. #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
  281. #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
  282. #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
  283. #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
  284. #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
  285. #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
  286. #define IS_HAL_REMAPDMA IS_DMA_REMAP
  287. #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
  288. #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
  289. #if defined(STM32L4)
  290. #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
  291. #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
  292. #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
  293. #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
  294. #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
  295. #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
  296. #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
  297. #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
  298. #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
  299. #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
  300. #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
  301. #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
  302. #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
  303. #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
  304. #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
  305. #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
  306. #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
  307. #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
  308. #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
  309. #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
  310. #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
  311. #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
  312. #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
  313. #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
  314. #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
  315. #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
  316. #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
  317. #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
  318. #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
  319. #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
  320. #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
  321. defined(STM32L4S7xx) || defined(STM32L4S9xx)
  322. #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
  323. #endif
  324. #endif /* STM32L4 */
  325. #if defined(STM32G0)
  326. #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
  327. #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
  328. #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
  329. #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
  330. #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
  331. #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
  332. #endif
  333. #if defined(STM32H7)
  334. #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
  335. #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
  336. #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
  337. #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
  338. #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
  339. #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
  340. #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
  341. #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
  342. #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
  343. #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
  344. #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
  345. #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
  346. #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
  347. #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
  348. #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
  349. #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
  350. #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
  351. #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
  352. #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
  353. #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
  354. #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
  355. #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
  356. #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
  357. #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
  358. #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
  359. #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
  360. #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
  361. #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
  362. #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
  363. #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
  364. #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
  365. #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
  366. #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
  367. #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
  368. #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
  369. #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
  370. #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
  371. #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
  372. #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
  373. #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
  374. #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
  375. #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
  376. #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
  377. #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
  378. #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
  379. #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
  380. #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
  381. #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
  382. #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
  383. #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
  384. #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
  385. #endif /* STM32H7 */
  386. #if defined(STM32U5)
  387. #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
  388. #endif /* STM32U5 */
  389. /**
  390. * @}
  391. */
  392. /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
  393. * @{
  394. */
  395. #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
  396. #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
  397. #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
  398. #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
  399. #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
  400. #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
  401. #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
  402. #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
  403. #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
  404. #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
  405. #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
  406. #define OBEX_PCROP OPTIONBYTE_PCROP
  407. #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
  408. #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
  409. #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
  410. #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
  411. #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
  412. #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
  413. #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
  414. #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
  415. #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
  416. #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
  417. #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
  418. #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
  419. #define PAGESIZE FLASH_PAGE_SIZE
  420. #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
  421. #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
  422. #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
  423. #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
  424. #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
  425. #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
  426. #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
  427. #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
  428. #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
  429. #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
  430. #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
  431. #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
  432. #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
  433. #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
  434. #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
  435. #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
  436. #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
  437. #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
  438. #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
  439. #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
  440. #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
  441. #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
  442. #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
  443. #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
  444. #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
  445. #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
  446. #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
  447. #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
  448. #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
  449. #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
  450. #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
  451. #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
  452. #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
  453. #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
  454. #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
  455. #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
  456. #define OB_WDG_SW OB_IWDG_SW
  457. #define OB_WDG_HW OB_IWDG_HW
  458. #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
  459. #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
  460. #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
  461. #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
  462. #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
  463. #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
  464. #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
  465. #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
  466. #if defined(STM32G0) || defined(STM32C0)
  467. #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
  468. #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
  469. #else
  470. #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
  471. #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
  472. #endif
  473. #if defined(STM32H7)
  474. #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
  475. #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
  476. #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
  477. #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
  478. #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
  479. #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
  480. #define FLASH_FLAG_WDW FLASH_FLAG_WBNE
  481. #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
  482. #endif /* STM32H7 */
  483. #if defined(STM32U5)
  484. #define OB_USER_nRST_STOP OB_USER_NRST_STOP
  485. #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
  486. #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
  487. #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
  488. #define OB_USER_nBOOT0 OB_USER_NBOOT0
  489. #define OB_nBOOT0_RESET OB_NBOOT0_RESET
  490. #define OB_nBOOT0_SET OB_NBOOT0_SET
  491. #define OB_USER_SRAM134_RST OB_USER_SRAM_RST
  492. #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
  493. #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
  494. #endif /* STM32U5 */
  495. #if defined(STM32U0)
  496. #define OB_USER_nRST_STOP OB_USER_NRST_STOP
  497. #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
  498. #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
  499. #define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
  500. #define OB_USER_nBOOT0 OB_USER_NBOOT0
  501. #define OB_USER_nBOOT1 OB_USER_NBOOT1
  502. #define OB_nBOOT0_RESET OB_NBOOT0_RESET
  503. #define OB_nBOOT0_SET OB_NBOOT0_SET
  504. #endif /* STM32U0 */
  505. /**
  506. * @}
  507. */
  508. /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
  509. * @{
  510. */
  511. #if defined(STM32H7)
  512. #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
  513. #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
  514. #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
  515. #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
  516. #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
  517. #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
  518. #endif /* STM32H7 */
  519. /**
  520. * @}
  521. */
  522. /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
  523. * @{
  524. */
  525. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
  526. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
  527. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
  528. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
  529. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
  530. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
  531. #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
  532. #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
  533. #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
  534. #if defined(STM32G4)
  535. #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
  536. #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
  537. #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
  538. #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
  539. #endif /* STM32G4 */
  540. #if defined(STM32H5)
  541. #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
  542. #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
  543. #define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
  544. #define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
  545. #define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
  546. #define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
  547. #define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
  548. #define SYSCFG_BREAK_PVD SBS_BREAK_PVD
  549. #define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
  550. #define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
  551. #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
  552. #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
  553. #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
  554. #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
  555. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
  556. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
  557. #define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
  558. #define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
  559. #define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
  560. #define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
  561. #define SYSCFG_ETH_MII SBS_ETH_MII
  562. #define SYSCFG_ETH_RMII SBS_ETH_RMII
  563. #define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
  564. #define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
  565. #define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
  566. #define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
  567. #define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
  568. #define SYSCFG_MPU_NSEC SBS_MPU_NSEC
  569. #define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
  570. #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
  571. #define SYSCFG_SAU SBS_SAU
  572. #define SYSCFG_MPU_SEC SBS_MPU_SEC
  573. #define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
  574. #define SYSCFG_LOCK_ALL SBS_LOCK_ALL
  575. #else
  576. #define SYSCFG_LOCK_ALL SBS_LOCK_ALL
  577. #endif /* __ARM_FEATURE_CMSE */
  578. #define SYSCFG_CLK SBS_CLK
  579. #define SYSCFG_CLASSB SBS_CLASSB
  580. #define SYSCFG_FPU SBS_FPU
  581. #define SYSCFG_ALL SBS_ALL
  582. #define SYSCFG_SEC SBS_SEC
  583. #define SYSCFG_NSEC SBS_NSEC
  584. #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
  585. #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
  586. #define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
  587. #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
  588. #define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
  589. #define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
  590. #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
  591. #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
  592. #define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
  593. #define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
  594. #define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
  595. #define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
  596. #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
  597. #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
  598. #define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
  599. #define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
  600. #define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
  601. #define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
  602. #define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
  603. #define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
  604. #define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
  605. #define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
  606. #define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
  607. #define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
  608. #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
  609. #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
  610. #define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
  611. #define HAL_SYSCFG_Lock HAL_SBS_Lock
  612. #define HAL_SYSCFG_GetLock HAL_SBS_GetLock
  613. #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
  614. #define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
  615. #define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
  616. #endif /* __ARM_FEATURE_CMSE */
  617. #endif /* STM32H5 */
  618. /**
  619. * @}
  620. */
  621. /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
  622. * @{
  623. */
  624. #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
  625. #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
  626. #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
  627. #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
  628. #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
  629. #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
  630. #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
  631. #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
  632. #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
  633. #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
  634. #endif
  635. /**
  636. * @}
  637. */
  638. /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
  639. * @{
  640. */
  641. #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
  642. #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
  643. /**
  644. * @}
  645. */
  646. /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
  647. * @{
  648. */
  649. #define GET_GPIO_SOURCE GPIO_GET_INDEX
  650. #define GET_GPIO_INDEX GPIO_GET_INDEX
  651. #if defined(STM32F4)
  652. #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
  653. #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
  654. #endif
  655. #if defined(STM32F7)
  656. #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
  657. #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
  658. #endif
  659. #if defined(STM32L4)
  660. #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
  661. #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
  662. #endif
  663. #if defined(STM32H7)
  664. #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
  665. #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
  666. #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
  667. #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
  668. #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
  669. #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
  670. #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
  671. defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
  672. #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
  673. #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
  674. #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
  675. #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
  676. STM32H757xx */
  677. #endif /* STM32H7 */
  678. #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
  679. #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
  680. #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
  681. #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
  682. defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
  683. #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
  684. #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
  685. #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
  686. #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
  687. #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
  688. #if defined(STM32L1)
  689. #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
  690. #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
  691. #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
  692. #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
  693. #endif /* STM32L1 */
  694. #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
  695. #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
  696. #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
  697. #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
  698. #endif /* STM32F0 || STM32F3 || STM32F1 */
  699. #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
  700. #if defined(STM32U5) || defined(STM32H5)
  701. #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
  702. #endif /* STM32U5 || STM32H5 */
  703. #if defined(STM32U5)
  704. #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
  705. #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
  706. #endif /* STM32U5 */
  707. /**
  708. * @}
  709. */
  710. /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
  711. * @{
  712. */
  713. #if defined(STM32U5)
  714. #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
  715. #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
  716. #endif /* STM32U5 */
  717. #if defined(STM32H5)
  718. #define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
  719. #define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
  720. #define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
  721. #endif /* STM32H5 */
  722. #if defined(STM32H5) || defined(STM32U5)
  723. #define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
  724. #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
  725. #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
  726. #define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
  727. #define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
  728. #define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
  729. #define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
  730. #define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
  731. #define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
  732. #define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
  733. #endif /* STM32H5 || STM32U5 */
  734. /**
  735. * @}
  736. */
  737. /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
  738. * @{
  739. */
  740. #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
  741. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
  742. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
  743. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
  744. #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
  745. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
  746. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
  747. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
  748. #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
  749. #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
  750. #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
  751. #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
  752. #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
  753. #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
  754. #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
  755. #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
  756. #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
  757. #if defined(STM32G4)
  758. #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
  759. #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
  760. #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
  761. #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
  762. #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
  763. #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
  764. #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
  765. #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
  766. #endif /* STM32G4 */
  767. #if defined(STM32H7)
  768. #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
  769. #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
  770. #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
  771. #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
  772. #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
  773. #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
  774. #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
  775. #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
  776. #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
  777. #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
  778. #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
  779. #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
  780. #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
  781. #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
  782. #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
  783. #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
  784. #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
  785. #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
  786. #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
  787. #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
  788. #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
  789. #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
  790. #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
  791. #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
  792. #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
  793. #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
  794. #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
  795. #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
  796. #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
  797. #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
  798. #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
  799. #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
  800. #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
  801. #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
  802. #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
  803. #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
  804. #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
  805. #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
  806. #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
  807. #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
  808. #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
  809. #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
  810. #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
  811. #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
  812. #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
  813. #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
  814. #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
  815. #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
  816. #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
  817. #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
  818. #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
  819. #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
  820. #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
  821. #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
  822. #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
  823. #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
  824. #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
  825. #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
  826. #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
  827. #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
  828. #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
  829. #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
  830. #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
  831. #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
  832. #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
  833. #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
  834. #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
  835. #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
  836. #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
  837. #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
  838. #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
  839. #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
  840. #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
  841. #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
  842. #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
  843. #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
  844. #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
  845. #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
  846. #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
  847. #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
  848. #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
  849. #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
  850. #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
  851. #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
  852. #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
  853. #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
  854. #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
  855. #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
  856. #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
  857. #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
  858. #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
  859. #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
  860. #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
  861. #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
  862. #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
  863. #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
  864. #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
  865. #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
  866. #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
  867. #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
  868. #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
  869. #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
  870. #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
  871. #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
  872. #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
  873. #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
  874. #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
  875. #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
  876. #endif /* STM32H7 */
  877. #if defined(STM32F3)
  878. /** @brief Constants defining available sources associated to external events.
  879. */
  880. #define HRTIM_EVENTSRC_1 (0x00000000U)
  881. #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
  882. #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
  883. #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
  884. /** @brief Constants defining the DLL calibration periods (in micro seconds)
  885. */
  886. #define HRTIM_CALIBRATIONRATE_7300 0x00000000U
  887. #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
  888. #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
  889. #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
  890. #endif /* STM32F3 */
  891. /**
  892. * @}
  893. */
  894. /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
  895. * @{
  896. */
  897. #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
  898. #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
  899. #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
  900. #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
  901. #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
  902. #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
  903. #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
  904. #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
  905. #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
  906. defined(STM32L1) || defined(STM32F7)
  907. #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
  908. #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
  909. #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
  910. #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
  911. #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
  912. #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
  913. #endif
  914. /**
  915. * @}
  916. */
  917. /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
  918. * @{
  919. */
  920. #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
  921. #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
  922. /**
  923. * @}
  924. */
  925. /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
  926. * @{
  927. */
  928. #define KR_KEY_RELOAD IWDG_KEY_RELOAD
  929. #define KR_KEY_ENABLE IWDG_KEY_ENABLE
  930. #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
  931. #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
  932. /**
  933. * @}
  934. */
  935. /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
  936. * @{
  937. */
  938. #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
  939. #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
  940. #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
  941. #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
  942. #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
  943. #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
  944. #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
  945. #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
  946. #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
  947. #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
  948. #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
  949. /* The following 3 definition have also been present in a temporary version of lptim.h */
  950. /* They need to be renamed also to the right name, just in case */
  951. #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
  952. #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
  953. #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
  954. /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
  955. * @{
  956. */
  957. #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
  958. /**
  959. * @}
  960. */
  961. #if defined(STM32U5)
  962. #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
  963. #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
  964. #define LPTIM_CHANNEL_ALL 0x00000000U
  965. #endif /* STM32U5 */
  966. /**
  967. * @}
  968. */
  969. /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
  970. * @{
  971. */
  972. #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
  973. #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
  974. #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
  975. #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
  976. #define NAND_AddressTypedef NAND_AddressTypeDef
  977. #define __ARRAY_ADDRESS ARRAY_ADDRESS
  978. #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
  979. #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
  980. #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
  981. #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
  982. /**
  983. * @}
  984. */
  985. /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
  986. * @{
  987. */
  988. #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
  989. #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
  990. #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
  991. #define NOR_ERROR HAL_NOR_STATUS_ERROR
  992. #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
  993. #define __NOR_WRITE NOR_WRITE
  994. #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
  995. /**
  996. * @}
  997. */
  998. /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
  999. * @{
  1000. */
  1001. #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
  1002. #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
  1003. #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
  1004. #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
  1005. #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
  1006. #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
  1007. #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
  1008. #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
  1009. #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
  1010. #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
  1011. #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
  1012. #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
  1013. #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
  1014. #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
  1015. #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
  1016. #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
  1017. #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
  1018. #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
  1019. #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
  1020. #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
  1021. #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
  1022. #endif
  1023. #if defined(STM32L4) || defined(STM32L5)
  1024. #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
  1025. #elif defined(STM32G4)
  1026. #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
  1027. #endif
  1028. /**
  1029. * @}
  1030. */
  1031. /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
  1032. * @{
  1033. */
  1034. #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
  1035. #if defined(STM32H7)
  1036. #define I2S_IT_TXE I2S_IT_TXP
  1037. #define I2S_IT_RXNE I2S_IT_RXP
  1038. #define I2S_FLAG_TXE I2S_FLAG_TXP
  1039. #define I2S_FLAG_RXNE I2S_FLAG_RXP
  1040. #endif
  1041. #if defined(STM32F7)
  1042. #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
  1043. #endif
  1044. /**
  1045. * @}
  1046. */
  1047. /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
  1048. * @{
  1049. */
  1050. /* Compact Flash-ATA registers description */
  1051. #define CF_DATA ATA_DATA
  1052. #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
  1053. #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
  1054. #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
  1055. #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
  1056. #define CF_CARD_HEAD ATA_CARD_HEAD
  1057. #define CF_STATUS_CMD ATA_STATUS_CMD
  1058. #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
  1059. #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
  1060. /* Compact Flash-ATA commands */
  1061. #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
  1062. #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
  1063. #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
  1064. #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
  1065. #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
  1066. #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
  1067. #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
  1068. #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
  1069. #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
  1070. /**
  1071. * @}
  1072. */
  1073. /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
  1074. * @{
  1075. */
  1076. #define FORMAT_BIN RTC_FORMAT_BIN
  1077. #define FORMAT_BCD RTC_FORMAT_BCD
  1078. #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
  1079. #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
  1080. #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
  1081. #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
  1082. #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
  1083. #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
  1084. #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
  1085. #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
  1086. #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
  1087. #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
  1088. #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
  1089. #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
  1090. #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
  1091. #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
  1092. #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
  1093. #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
  1094. #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
  1095. #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
  1096. #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
  1097. #if defined(STM32H5) || defined(STM32H7RS)
  1098. #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
  1099. #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
  1100. #endif /* STM32H5 || STM32H7RS */
  1101. #if defined(STM32WBA)
  1102. #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
  1103. #define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
  1104. #define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
  1105. #define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
  1106. #define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
  1107. #define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
  1108. #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
  1109. #endif /* STM32WBA */
  1110. #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
  1111. #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
  1112. #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
  1113. #endif /* STM32H5 || STM32WBA || STM32H7RS */
  1114. #if defined(STM32F7)
  1115. #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
  1116. #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
  1117. #endif /* STM32F7 */
  1118. #if defined(STM32H7)
  1119. #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
  1120. #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
  1121. #endif /* STM32H7 */
  1122. #if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
  1123. #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
  1124. #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
  1125. #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
  1126. #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
  1127. #endif /* STM32F7 || STM32H7 || STM32L0 */
  1128. /**
  1129. * @}
  1130. */
  1131. /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
  1132. * @{
  1133. */
  1134. #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
  1135. #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
  1136. #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
  1137. #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
  1138. #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
  1139. #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
  1140. #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
  1141. #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
  1142. #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
  1143. #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
  1144. /**
  1145. * @}
  1146. */
  1147. /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
  1148. * @{
  1149. */
  1150. #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
  1151. #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
  1152. #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
  1153. #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
  1154. #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
  1155. #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
  1156. #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
  1157. #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
  1158. #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
  1159. #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
  1160. #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
  1161. /**
  1162. * @}
  1163. */
  1164. /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
  1165. * @{
  1166. */
  1167. #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
  1168. #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
  1169. #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
  1170. #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
  1171. #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
  1172. #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
  1173. #if defined(STM32H7)
  1174. #define SPI_FLAG_TXE SPI_FLAG_TXP
  1175. #define SPI_FLAG_RXNE SPI_FLAG_RXP
  1176. #define SPI_IT_TXE SPI_IT_TXP
  1177. #define SPI_IT_RXNE SPI_IT_RXP
  1178. #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
  1179. #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
  1180. #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
  1181. #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
  1182. #endif /* STM32H7 */
  1183. /**
  1184. * @}
  1185. */
  1186. /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
  1187. * @{
  1188. */
  1189. #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
  1190. #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
  1191. #define TIM_DMABase_CR1 TIM_DMABASE_CR1
  1192. #define TIM_DMABase_CR2 TIM_DMABASE_CR2
  1193. #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
  1194. #define TIM_DMABase_DIER TIM_DMABASE_DIER
  1195. #define TIM_DMABase_SR TIM_DMABASE_SR
  1196. #define TIM_DMABase_EGR TIM_DMABASE_EGR
  1197. #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
  1198. #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
  1199. #define TIM_DMABase_CCER TIM_DMABASE_CCER
  1200. #define TIM_DMABase_CNT TIM_DMABASE_CNT
  1201. #define TIM_DMABase_PSC TIM_DMABASE_PSC
  1202. #define TIM_DMABase_ARR TIM_DMABASE_ARR
  1203. #define TIM_DMABase_RCR TIM_DMABASE_RCR
  1204. #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
  1205. #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
  1206. #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
  1207. #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
  1208. #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
  1209. #define TIM_DMABase_DCR TIM_DMABASE_DCR
  1210. #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
  1211. #define TIM_DMABase_OR1 TIM_DMABASE_OR1
  1212. #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
  1213. #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
  1214. #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
  1215. #define TIM_DMABase_OR2 TIM_DMABASE_OR2
  1216. #define TIM_DMABase_OR3 TIM_DMABASE_OR3
  1217. #define TIM_DMABase_OR TIM_DMABASE_OR
  1218. #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
  1219. #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
  1220. #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
  1221. #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
  1222. #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
  1223. #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
  1224. #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
  1225. #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
  1226. #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
  1227. #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
  1228. #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
  1229. #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
  1230. #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
  1231. #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
  1232. #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
  1233. #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
  1234. #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
  1235. #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
  1236. #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
  1237. #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
  1238. #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
  1239. #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
  1240. #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
  1241. #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
  1242. #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
  1243. #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
  1244. #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
  1245. #if defined(STM32L0)
  1246. #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
  1247. #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
  1248. #endif
  1249. #if defined(STM32F3)
  1250. #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
  1251. #endif
  1252. #if defined(STM32H7)
  1253. #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
  1254. #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
  1255. #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
  1256. #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
  1257. #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
  1258. #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
  1259. #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
  1260. #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
  1261. #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
  1262. #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
  1263. #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
  1264. #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
  1265. #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
  1266. #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
  1267. #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
  1268. #endif
  1269. #if defined(STM32U5)
  1270. #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
  1271. #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
  1272. #endif
  1273. /**
  1274. * @}
  1275. */
  1276. /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
  1277. * @{
  1278. */
  1279. #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
  1280. #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
  1281. /**
  1282. * @}
  1283. */
  1284. /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
  1285. * @{
  1286. */
  1287. #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
  1288. #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
  1289. #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
  1290. #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
  1291. #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
  1292. #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
  1293. #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
  1294. #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
  1295. #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
  1296. #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
  1297. #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
  1298. #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
  1299. #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
  1300. #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
  1301. #define __DIV_LPUART UART_DIV_LPUART
  1302. #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
  1303. #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
  1304. /**
  1305. * @}
  1306. */
  1307. /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
  1308. * @{
  1309. */
  1310. #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
  1311. #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
  1312. #define USARTNACK_ENABLED USART_NACK_ENABLE
  1313. #define USARTNACK_DISABLED USART_NACK_DISABLE
  1314. /**
  1315. * @}
  1316. */
  1317. /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
  1318. * @{
  1319. */
  1320. #define CFR_BASE WWDG_CFR_BASE
  1321. /**
  1322. * @}
  1323. */
  1324. /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
  1325. * @{
  1326. */
  1327. #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
  1328. #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
  1329. #define CAN_IT_RQCP0 CAN_IT_TME
  1330. #define CAN_IT_RQCP1 CAN_IT_TME
  1331. #define CAN_IT_RQCP2 CAN_IT_TME
  1332. #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
  1333. #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
  1334. #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
  1335. #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
  1336. #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
  1337. /**
  1338. * @}
  1339. */
  1340. /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
  1341. * @{
  1342. */
  1343. #define VLAN_TAG ETH_VLAN_TAG
  1344. #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
  1345. #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
  1346. #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
  1347. #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
  1348. #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
  1349. #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
  1350. #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
  1351. #define ETH_MMCCR 0x00000100U
  1352. #define ETH_MMCRIR 0x00000104U
  1353. #define ETH_MMCTIR 0x00000108U
  1354. #define ETH_MMCRIMR 0x0000010CU
  1355. #define ETH_MMCTIMR 0x00000110U
  1356. #define ETH_MMCTGFSCCR 0x0000014CU
  1357. #define ETH_MMCTGFMSCCR 0x00000150U
  1358. #define ETH_MMCTGFCR 0x00000168U
  1359. #define ETH_MMCRFCECR 0x00000194U
  1360. #define ETH_MMCRFAECR 0x00000198U
  1361. #define ETH_MMCRGUFCR 0x000001C4U
  1362. #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
  1363. #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
  1364. #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
  1365. #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
  1366. #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
  1367. the MAC transmitter) */
  1368. #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
  1369. MAC transmitter */
  1370. #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
  1371. or flushing the TxFIFO */
  1372. #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
  1373. #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
  1374. #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
  1375. of previous frame or IFG/backoff period to be over */
  1376. #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
  1377. transmitting a Pause control frame (in full duplex mode) */
  1378. #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
  1379. frame for transmission */
  1380. #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
  1381. #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
  1382. #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
  1383. de-activate threshold */
  1384. #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
  1385. activate threshold */
  1386. #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
  1387. #if defined(STM32F1)
  1388. #else
  1389. #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
  1390. #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
  1391. #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
  1392. (or time-stamp) */
  1393. #endif
  1394. #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
  1395. status */
  1396. #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
  1397. #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
  1398. #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
  1399. #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
  1400. #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
  1401. #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
  1402. #define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
  1403. /**
  1404. * @}
  1405. */
  1406. /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
  1407. * @{
  1408. */
  1409. #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
  1410. #define DCMI_IT_OVF DCMI_IT_OVR
  1411. #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
  1412. #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
  1413. #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
  1414. #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
  1415. #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
  1416. /**
  1417. * @}
  1418. */
  1419. #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
  1420. || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
  1421. || defined(STM32H7)
  1422. /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
  1423. * @{
  1424. */
  1425. #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
  1426. #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
  1427. #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
  1428. #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
  1429. #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
  1430. #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
  1431. #define CM_RGB888 DMA2D_INPUT_RGB888
  1432. #define CM_RGB565 DMA2D_INPUT_RGB565
  1433. #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
  1434. #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
  1435. #define CM_L8 DMA2D_INPUT_L8
  1436. #define CM_AL44 DMA2D_INPUT_AL44
  1437. #define CM_AL88 DMA2D_INPUT_AL88
  1438. #define CM_L4 DMA2D_INPUT_L4
  1439. #define CM_A8 DMA2D_INPUT_A8
  1440. #define CM_A4 DMA2D_INPUT_A4
  1441. /**
  1442. * @}
  1443. */
  1444. #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
  1445. #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
  1446. || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
  1447. || defined(STM32H7) || defined(STM32U5)
  1448. /** @defgroup DMA2D_Aliases DMA2D API Aliases
  1449. * @{
  1450. */
  1451. #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
  1452. for compatibility with legacy code */
  1453. /**
  1454. * @}
  1455. */
  1456. #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
  1457. /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
  1458. * @{
  1459. */
  1460. /**
  1461. * @}
  1462. */
  1463. /* Exported functions --------------------------------------------------------*/
  1464. /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
  1465. * @{
  1466. */
  1467. #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
  1468. /**
  1469. * @}
  1470. */
  1471. /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
  1472. * @{
  1473. */
  1474. #if defined(STM32U5)
  1475. #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
  1476. #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
  1477. #endif /* STM32U5 */
  1478. /**
  1479. * @}
  1480. */
  1481. #if !defined(STM32F2)
  1482. /** @defgroup HASH_alias HASH API alias
  1483. * @{
  1484. */
  1485. #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
  1486. /**
  1487. *
  1488. * @}
  1489. */
  1490. #endif /* STM32F2 */
  1491. /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
  1492. * @{
  1493. */
  1494. #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
  1495. #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
  1496. #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
  1497. #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
  1498. #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
  1499. #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
  1500. /*HASH Algorithm Selection*/
  1501. #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
  1502. #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
  1503. #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
  1504. #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
  1505. #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
  1506. #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
  1507. #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
  1508. #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
  1509. #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
  1510. #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
  1511. #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
  1512. #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
  1513. #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
  1514. #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
  1515. #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
  1516. #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
  1517. #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
  1518. #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
  1519. #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
  1520. #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
  1521. #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
  1522. #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
  1523. #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
  1524. #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
  1525. #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
  1526. #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
  1527. /**
  1528. * @}
  1529. */
  1530. /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
  1531. * @{
  1532. */
  1533. #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
  1534. #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
  1535. #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
  1536. #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
  1537. #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
  1538. #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
  1539. #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
  1540. )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
  1541. HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
  1542. #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
  1543. #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
  1544. #if defined(STM32L0)
  1545. #else
  1546. #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
  1547. #endif
  1548. #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
  1549. #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
  1550. )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
  1551. HAL_ADCEx_DisableVREFINTTempSensor())
  1552. #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
  1553. defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
  1554. #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
  1555. #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
  1556. #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
  1557. #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
  1558. #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
  1559. /**
  1560. * @}
  1561. */
  1562. /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
  1563. * @{
  1564. */
  1565. #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
  1566. #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
  1567. #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
  1568. #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
  1569. #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
  1570. #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
  1571. #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
  1572. /**
  1573. * @}
  1574. */
  1575. /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
  1576. * @{
  1577. */
  1578. #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
  1579. #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
  1580. #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
  1581. #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
  1582. #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
  1583. HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
  1584. HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
  1585. #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
  1586. defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
  1587. defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
  1588. #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
  1589. #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
  1590. #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
  1591. #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
  1592. #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
  1593. STM32L4 || STM32L5 || STM32G4 || STM32L1 */
  1594. #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
  1595. defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
  1596. #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
  1597. #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
  1598. #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
  1599. #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
  1600. #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
  1601. #if defined(STM32F4)
  1602. #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
  1603. #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
  1604. #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
  1605. #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
  1606. #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
  1607. #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
  1608. #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
  1609. #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
  1610. #endif /* STM32F4 */
  1611. /**
  1612. * @}
  1613. */
  1614. /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
  1615. * @{
  1616. */
  1617. #if defined(STM32G0)
  1618. #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
  1619. #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
  1620. #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
  1621. #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
  1622. #endif
  1623. #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
  1624. #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
  1625. #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
  1626. #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
  1627. #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
  1628. #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
  1629. #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
  1630. #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
  1631. #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
  1632. #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
  1633. #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
  1634. #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
  1635. #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
  1636. #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
  1637. #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
  1638. #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
  1639. #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
  1640. #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
  1641. #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
  1642. #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
  1643. #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
  1644. #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
  1645. #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
  1646. #define CR_OFFSET_BB PWR_CR_OFFSET_BB
  1647. #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
  1648. #define PMODE_BIT_NUMBER VOS_BIT_NUMBER
  1649. #define CR_PMODE_BB CR_VOS_BB
  1650. #define DBP_BitNumber DBP_BIT_NUMBER
  1651. #define PVDE_BitNumber PVDE_BIT_NUMBER
  1652. #define PMODE_BitNumber PMODE_BIT_NUMBER
  1653. #define EWUP_BitNumber EWUP_BIT_NUMBER
  1654. #define FPDS_BitNumber FPDS_BIT_NUMBER
  1655. #define ODEN_BitNumber ODEN_BIT_NUMBER
  1656. #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
  1657. #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
  1658. #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
  1659. #define BRE_BitNumber BRE_BIT_NUMBER
  1660. #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
  1661. #if defined (STM32U5)
  1662. #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
  1663. #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
  1664. #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
  1665. #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
  1666. #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
  1667. #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
  1668. #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
  1669. #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
  1670. #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
  1671. #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
  1672. #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
  1673. #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
  1674. #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
  1675. #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
  1676. #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
  1677. #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
  1678. #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
  1679. #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
  1680. #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
  1681. #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
  1682. #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
  1683. #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
  1684. #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
  1685. #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
  1686. #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
  1687. #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
  1688. #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
  1689. #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
  1690. #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
  1691. #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
  1692. #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
  1693. #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
  1694. #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
  1695. #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
  1696. #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
  1697. #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
  1698. #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
  1699. #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
  1700. #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
  1701. #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
  1702. #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
  1703. #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
  1704. #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
  1705. #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
  1706. #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
  1707. #define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
  1708. #define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
  1709. #define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
  1710. #define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
  1711. #define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
  1712. #define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
  1713. #define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
  1714. #define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
  1715. #define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
  1716. #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
  1717. #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
  1718. #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
  1719. #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
  1720. #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
  1721. #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
  1722. #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
  1723. #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
  1724. #define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
  1725. #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
  1726. #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
  1727. #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
  1728. #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
  1729. #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
  1730. #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
  1731. #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
  1732. #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
  1733. #define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
  1734. #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
  1735. #endif
  1736. /**
  1737. * @}
  1738. */
  1739. /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
  1740. * @{
  1741. */
  1742. #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
  1743. #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
  1744. #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
  1745. #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
  1746. #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
  1747. #endif /* STM32H5 || STM32WBA || STM32H7RS */
  1748. /**
  1749. * @}
  1750. */
  1751. /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
  1752. * @{
  1753. */
  1754. #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
  1755. #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
  1756. #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
  1757. /**
  1758. * @}
  1759. */
  1760. /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
  1761. * @{
  1762. */
  1763. #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
  1764. /**
  1765. * @}
  1766. */
  1767. /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
  1768. * @{
  1769. */
  1770. #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
  1771. #define HAL_TIM_DMAError TIM_DMAError
  1772. #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
  1773. #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
  1774. #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
  1775. defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
  1776. #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
  1777. #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
  1778. #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
  1779. #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
  1780. #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
  1781. #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
  1782. #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
  1783. /**
  1784. * @}
  1785. */
  1786. /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
  1787. * @{
  1788. */
  1789. #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
  1790. /**
  1791. * @}
  1792. */
  1793. /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
  1794. * @{
  1795. */
  1796. #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
  1797. #define HAL_LTDC_Relaod HAL_LTDC_Reload
  1798. #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
  1799. #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
  1800. /**
  1801. * @}
  1802. */
  1803. /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
  1804. * @{
  1805. */
  1806. /**
  1807. * @}
  1808. */
  1809. /* Exported macros ------------------------------------------------------------*/
  1810. /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
  1811. * @{
  1812. */
  1813. #define AES_IT_CC CRYP_IT_CC
  1814. #define AES_IT_ERR CRYP_IT_ERR
  1815. #define AES_FLAG_CCF CRYP_FLAG_CCF
  1816. /**
  1817. * @}
  1818. */
  1819. /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
  1820. * @{
  1821. */
  1822. #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
  1823. #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
  1824. #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
  1825. #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
  1826. #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
  1827. #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
  1828. #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
  1829. #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
  1830. #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
  1831. #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
  1832. #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
  1833. #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
  1834. #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
  1835. #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
  1836. #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
  1837. #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
  1838. #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
  1839. #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
  1840. #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
  1841. /**
  1842. * @}
  1843. */
  1844. /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
  1845. * @{
  1846. */
  1847. #define __ADC_ENABLE __HAL_ADC_ENABLE
  1848. #define __ADC_DISABLE __HAL_ADC_DISABLE
  1849. #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
  1850. #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
  1851. #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
  1852. #define __ADC_IS_ENABLED ADC_IS_ENABLE
  1853. #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
  1854. #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
  1855. #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
  1856. #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
  1857. #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
  1858. #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
  1859. #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
  1860. #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
  1861. #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
  1862. #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
  1863. #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
  1864. #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
  1865. #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
  1866. #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
  1867. #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
  1868. #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
  1869. #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
  1870. #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
  1871. #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
  1872. #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
  1873. #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
  1874. #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
  1875. #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
  1876. #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
  1877. #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
  1878. #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
  1879. #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
  1880. #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
  1881. #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
  1882. #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
  1883. #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
  1884. #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
  1885. #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
  1886. #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
  1887. #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
  1888. #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
  1889. #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
  1890. #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
  1891. #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
  1892. #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
  1893. #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
  1894. #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
  1895. #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
  1896. #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
  1897. #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
  1898. #define __HAL_ADC_SQR1 ADC_SQR1
  1899. #define __HAL_ADC_SMPR1 ADC_SMPR1
  1900. #define __HAL_ADC_SMPR2 ADC_SMPR2
  1901. #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
  1902. #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
  1903. #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
  1904. #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
  1905. #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
  1906. #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
  1907. #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
  1908. #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
  1909. #define __HAL_ADC_JSQR ADC_JSQR
  1910. #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
  1911. #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
  1912. #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
  1913. #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
  1914. #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
  1915. #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
  1916. #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
  1917. #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
  1918. /**
  1919. * @}
  1920. */
  1921. /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
  1922. * @{
  1923. */
  1924. #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
  1925. #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
  1926. #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
  1927. #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
  1928. /**
  1929. * @}
  1930. */
  1931. /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
  1932. * @{
  1933. */
  1934. #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
  1935. #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
  1936. #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
  1937. #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
  1938. #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
  1939. #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
  1940. #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
  1941. #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
  1942. #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
  1943. #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
  1944. #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
  1945. #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
  1946. #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
  1947. #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
  1948. #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
  1949. #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
  1950. #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
  1951. #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
  1952. #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
  1953. #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
  1954. #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
  1955. #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
  1956. #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
  1957. #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
  1958. #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
  1959. #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
  1960. #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
  1961. #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
  1962. #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
  1963. #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
  1964. #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
  1965. #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
  1966. #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
  1967. #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
  1968. #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
  1969. #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
  1970. #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
  1971. #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
  1972. #if defined(STM32H7)
  1973. #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
  1974. #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
  1975. #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
  1976. #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
  1977. #else
  1978. #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
  1979. #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
  1980. #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
  1981. #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
  1982. #endif /* STM32H7 */
  1983. #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
  1984. #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
  1985. #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
  1986. #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
  1987. #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
  1988. #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
  1989. #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
  1990. #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
  1991. #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
  1992. #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
  1993. #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
  1994. #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
  1995. /**
  1996. * @}
  1997. */
  1998. /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
  1999. * @{
  2000. */
  2001. #if defined(STM32F3)
  2002. #define COMP_START __HAL_COMP_ENABLE
  2003. #define COMP_STOP __HAL_COMP_DISABLE
  2004. #define COMP_LOCK __HAL_COMP_LOCK
  2005. #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
  2006. defined(STM32F334x8) || defined(STM32F328xx)
  2007. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
  2008. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
  2009. __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
  2010. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
  2011. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
  2012. __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
  2013. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
  2014. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
  2015. __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
  2016. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
  2017. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
  2018. __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
  2019. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
  2020. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
  2021. __HAL_COMP_COMP6_EXTI_ENABLE_IT())
  2022. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
  2023. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
  2024. __HAL_COMP_COMP6_EXTI_DISABLE_IT())
  2025. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
  2026. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
  2027. __HAL_COMP_COMP6_EXTI_GET_FLAG())
  2028. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
  2029. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
  2030. __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
  2031. #endif
  2032. #if defined(STM32F302xE) || defined(STM32F302xC)
  2033. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  2034. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
  2035. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
  2036. __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
  2037. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  2038. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
  2039. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
  2040. __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
  2041. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  2042. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
  2043. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
  2044. __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
  2045. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  2046. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
  2047. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
  2048. __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
  2049. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  2050. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
  2051. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
  2052. __HAL_COMP_COMP6_EXTI_ENABLE_IT())
  2053. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  2054. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
  2055. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
  2056. __HAL_COMP_COMP6_EXTI_DISABLE_IT())
  2057. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  2058. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
  2059. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
  2060. __HAL_COMP_COMP6_EXTI_GET_FLAG())
  2061. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  2062. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
  2063. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
  2064. __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
  2065. #endif
  2066. #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
  2067. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  2068. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
  2069. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
  2070. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
  2071. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
  2072. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
  2073. __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
  2074. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  2075. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
  2076. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
  2077. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
  2078. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
  2079. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
  2080. __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
  2081. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  2082. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
  2083. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
  2084. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
  2085. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
  2086. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
  2087. __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
  2088. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  2089. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
  2090. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
  2091. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
  2092. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
  2093. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
  2094. __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
  2095. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  2096. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
  2097. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
  2098. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
  2099. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
  2100. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
  2101. __HAL_COMP_COMP7_EXTI_ENABLE_IT())
  2102. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  2103. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
  2104. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
  2105. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
  2106. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
  2107. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
  2108. __HAL_COMP_COMP7_EXTI_DISABLE_IT())
  2109. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  2110. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
  2111. ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
  2112. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
  2113. ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
  2114. ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
  2115. __HAL_COMP_COMP7_EXTI_GET_FLAG())
  2116. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  2117. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
  2118. ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
  2119. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
  2120. ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
  2121. ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
  2122. __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
  2123. #endif
  2124. #if defined(STM32F373xC) ||defined(STM32F378xx)
  2125. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  2126. __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
  2127. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  2128. __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
  2129. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  2130. __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
  2131. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  2132. __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
  2133. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  2134. __HAL_COMP_COMP2_EXTI_ENABLE_IT())
  2135. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  2136. __HAL_COMP_COMP2_EXTI_DISABLE_IT())
  2137. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  2138. __HAL_COMP_COMP2_EXTI_GET_FLAG())
  2139. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  2140. __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
  2141. #endif
  2142. #else
  2143. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  2144. __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
  2145. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  2146. __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
  2147. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  2148. __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
  2149. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  2150. __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
  2151. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  2152. __HAL_COMP_COMP2_EXTI_ENABLE_IT())
  2153. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  2154. __HAL_COMP_COMP2_EXTI_DISABLE_IT())
  2155. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  2156. __HAL_COMP_COMP2_EXTI_GET_FLAG())
  2157. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  2158. __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
  2159. #endif
  2160. #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
  2161. #if defined(STM32L0) || defined(STM32L4)
  2162. /* Note: On these STM32 families, the only argument of this macro */
  2163. /* is COMP_FLAG_LOCK. */
  2164. /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
  2165. /* argument. */
  2166. #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
  2167. #endif
  2168. /**
  2169. * @}
  2170. */
  2171. #if defined(STM32L0) || defined(STM32L4)
  2172. /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
  2173. * @{
  2174. */
  2175. #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
  2176. done into HAL_COMP_Init() */
  2177. #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
  2178. done into HAL_COMP_Init() */
  2179. /**
  2180. * @}
  2181. */
  2182. #endif
  2183. /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
  2184. * @{
  2185. */
  2186. #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
  2187. ((WAVE) == DAC_WAVE_NOISE)|| \
  2188. ((WAVE) == DAC_WAVE_TRIANGLE))
  2189. /**
  2190. * @}
  2191. */
  2192. /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
  2193. * @{
  2194. */
  2195. #define IS_WRPAREA IS_OB_WRPAREA
  2196. #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
  2197. #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
  2198. #define IS_TYPEERASE IS_FLASH_TYPEERASE
  2199. #define IS_NBSECTORS IS_FLASH_NBSECTORS
  2200. #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
  2201. /**
  2202. * @}
  2203. */
  2204. /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
  2205. * @{
  2206. */
  2207. #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
  2208. #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
  2209. #if defined(STM32F1)
  2210. #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
  2211. #else
  2212. #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
  2213. #endif /* STM32F1 */
  2214. #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
  2215. #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
  2216. #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
  2217. #define __HAL_I2C_SPEED I2C_SPEED
  2218. #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
  2219. #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
  2220. #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
  2221. #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
  2222. #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
  2223. #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
  2224. #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
  2225. #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
  2226. /**
  2227. * @}
  2228. */
  2229. /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
  2230. * @{
  2231. */
  2232. #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
  2233. #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
  2234. #if defined(STM32H7)
  2235. #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
  2236. #endif
  2237. /**
  2238. * @}
  2239. */
  2240. /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
  2241. * @{
  2242. */
  2243. #define __IRDA_DISABLE __HAL_IRDA_DISABLE
  2244. #define __IRDA_ENABLE __HAL_IRDA_ENABLE
  2245. #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
  2246. #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
  2247. #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
  2248. #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
  2249. #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
  2250. /**
  2251. * @}
  2252. */
  2253. /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
  2254. * @{
  2255. */
  2256. #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
  2257. #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
  2258. /**
  2259. * @}
  2260. */
  2261. /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
  2262. * @{
  2263. */
  2264. #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
  2265. #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
  2266. #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
  2267. /**
  2268. * @}
  2269. */
  2270. /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
  2271. * @{
  2272. */
  2273. #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
  2274. #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
  2275. #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
  2276. #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
  2277. #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
  2278. #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
  2279. #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
  2280. #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
  2281. #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
  2282. #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
  2283. #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
  2284. #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
  2285. #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
  2286. /**
  2287. * @}
  2288. */
  2289. /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
  2290. * @{
  2291. */
  2292. #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
  2293. #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
  2294. #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
  2295. #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
  2296. #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
  2297. #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
  2298. #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
  2299. #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
  2300. #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
  2301. #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
  2302. #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
  2303. #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
  2304. #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
  2305. #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
  2306. #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
  2307. #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
  2308. #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
  2309. __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
  2310. } while(0)
  2311. #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
  2312. #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
  2313. #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
  2314. #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
  2315. #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
  2316. #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
  2317. #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
  2318. #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
  2319. #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
  2320. HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
  2321. } while(0)
  2322. #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
  2323. HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
  2324. } while(0)
  2325. #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
  2326. #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
  2327. #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
  2328. #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
  2329. #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
  2330. #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
  2331. #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
  2332. #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
  2333. #if defined (STM32F4)
  2334. #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
  2335. #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
  2336. #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
  2337. #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
  2338. #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
  2339. #else
  2340. #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
  2341. #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
  2342. #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
  2343. #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
  2344. #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
  2345. #endif /* STM32F4 */
  2346. /**
  2347. * @}
  2348. */
  2349. /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
  2350. * @{
  2351. */
  2352. #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
  2353. #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
  2354. #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
  2355. #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
  2356. HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
  2357. #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
  2358. #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
  2359. #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
  2360. #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
  2361. #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
  2362. #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
  2363. #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
  2364. #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
  2365. #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
  2366. #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
  2367. #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
  2368. #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
  2369. #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
  2370. #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
  2371. #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
  2372. #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
  2373. #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
  2374. #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
  2375. #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
  2376. #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
  2377. #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
  2378. #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
  2379. #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
  2380. #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
  2381. #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
  2382. #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
  2383. #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
  2384. #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
  2385. #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
  2386. #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
  2387. #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
  2388. #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
  2389. #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
  2390. #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
  2391. #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
  2392. #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
  2393. #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
  2394. #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
  2395. #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
  2396. #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
  2397. #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
  2398. #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
  2399. #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
  2400. #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
  2401. #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
  2402. #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
  2403. #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
  2404. #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
  2405. #if defined(STM32C0)
  2406. #define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
  2407. #define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
  2408. #define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
  2409. #define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
  2410. #endif /* STM32C0 */
  2411. #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
  2412. #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
  2413. #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
  2414. #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
  2415. #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
  2416. #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
  2417. #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
  2418. #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
  2419. #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
  2420. #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
  2421. #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
  2422. #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
  2423. #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
  2424. #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
  2425. #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
  2426. #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
  2427. #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
  2428. #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
  2429. #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
  2430. #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
  2431. #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
  2432. #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
  2433. #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
  2434. #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
  2435. #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
  2436. #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
  2437. #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
  2438. #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
  2439. #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
  2440. #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
  2441. #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
  2442. #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
  2443. #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
  2444. #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
  2445. #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
  2446. #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
  2447. #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
  2448. #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
  2449. #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
  2450. #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
  2451. #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
  2452. #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
  2453. #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
  2454. #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
  2455. #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
  2456. #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
  2457. #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
  2458. #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
  2459. #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
  2460. #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
  2461. #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
  2462. #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
  2463. #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
  2464. #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
  2465. #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
  2466. #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
  2467. #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
  2468. #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
  2469. #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
  2470. #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
  2471. #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
  2472. #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
  2473. #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
  2474. #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
  2475. #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
  2476. #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
  2477. #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
  2478. #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
  2479. #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
  2480. #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
  2481. #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
  2482. #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
  2483. #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
  2484. #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
  2485. #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
  2486. #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
  2487. #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
  2488. #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
  2489. #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
  2490. #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
  2491. #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
  2492. #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
  2493. #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
  2494. #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
  2495. #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
  2496. #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
  2497. #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
  2498. #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
  2499. #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
  2500. #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
  2501. #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
  2502. #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
  2503. #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
  2504. #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
  2505. #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
  2506. #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
  2507. #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
  2508. #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
  2509. #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
  2510. #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
  2511. #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
  2512. #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
  2513. #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
  2514. #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
  2515. #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
  2516. #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
  2517. #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
  2518. #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
  2519. #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
  2520. #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
  2521. #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
  2522. #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
  2523. #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
  2524. #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
  2525. #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
  2526. #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
  2527. #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
  2528. #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
  2529. #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
  2530. #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
  2531. #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
  2532. #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
  2533. #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
  2534. #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
  2535. #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
  2536. #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
  2537. #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
  2538. #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
  2539. #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
  2540. #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
  2541. #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
  2542. #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
  2543. #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
  2544. #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
  2545. #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
  2546. #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
  2547. #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
  2548. #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
  2549. #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
  2550. #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
  2551. #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
  2552. #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
  2553. #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
  2554. #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
  2555. #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
  2556. #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
  2557. #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
  2558. #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
  2559. #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
  2560. #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
  2561. #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
  2562. #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
  2563. #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
  2564. #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
  2565. #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
  2566. #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
  2567. #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
  2568. #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
  2569. #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
  2570. #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
  2571. #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
  2572. #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
  2573. #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
  2574. #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
  2575. #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
  2576. #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
  2577. #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
  2578. #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
  2579. #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
  2580. #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
  2581. #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
  2582. #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
  2583. #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
  2584. #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
  2585. #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
  2586. #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
  2587. #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
  2588. #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
  2589. #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
  2590. #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
  2591. #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
  2592. #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
  2593. #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
  2594. #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
  2595. #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
  2596. #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
  2597. #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
  2598. #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
  2599. #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
  2600. #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
  2601. #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
  2602. #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
  2603. #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
  2604. #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
  2605. #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
  2606. #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
  2607. #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
  2608. #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
  2609. #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
  2610. #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
  2611. #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
  2612. #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
  2613. #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
  2614. #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
  2615. #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
  2616. #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
  2617. #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
  2618. #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
  2619. #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
  2620. #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
  2621. #if defined(STM32WB)
  2622. #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
  2623. #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
  2624. #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
  2625. #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
  2626. #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
  2627. #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
  2628. #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
  2629. #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
  2630. #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
  2631. #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
  2632. #define QSPI_IRQHandler QUADSPI_IRQHandler
  2633. #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
  2634. #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
  2635. #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
  2636. #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
  2637. #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
  2638. #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
  2639. #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
  2640. #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
  2641. #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
  2642. #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
  2643. #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
  2644. #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
  2645. #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
  2646. #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
  2647. #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
  2648. #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
  2649. #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
  2650. #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
  2651. #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
  2652. #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
  2653. #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
  2654. #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
  2655. #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
  2656. #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
  2657. #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
  2658. #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
  2659. #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
  2660. #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
  2661. #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
  2662. #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
  2663. #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
  2664. #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
  2665. #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
  2666. #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
  2667. #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
  2668. #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
  2669. #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
  2670. #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
  2671. #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
  2672. #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
  2673. #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
  2674. #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
  2675. #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
  2676. #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
  2677. #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
  2678. #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
  2679. #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
  2680. #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
  2681. #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
  2682. #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
  2683. #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
  2684. #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
  2685. #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
  2686. #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
  2687. #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
  2688. #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
  2689. #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
  2690. #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
  2691. #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
  2692. #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
  2693. #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
  2694. #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
  2695. #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
  2696. #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
  2697. #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
  2698. #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
  2699. #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
  2700. #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
  2701. #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
  2702. #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
  2703. #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
  2704. #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
  2705. #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
  2706. #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
  2707. #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
  2708. #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
  2709. #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
  2710. #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
  2711. #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
  2712. #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
  2713. #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
  2714. #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
  2715. #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
  2716. #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
  2717. #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
  2718. #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
  2719. #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
  2720. #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
  2721. #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
  2722. #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
  2723. #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
  2724. #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
  2725. #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
  2726. #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
  2727. #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
  2728. #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
  2729. #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
  2730. #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
  2731. #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
  2732. #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
  2733. #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
  2734. #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
  2735. #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
  2736. #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
  2737. #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
  2738. #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
  2739. #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
  2740. #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
  2741. #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
  2742. #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
  2743. #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
  2744. #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
  2745. #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
  2746. #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
  2747. #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
  2748. #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
  2749. #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
  2750. #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
  2751. #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
  2752. #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
  2753. #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
  2754. #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
  2755. #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
  2756. #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
  2757. #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
  2758. #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
  2759. #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
  2760. #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
  2761. #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
  2762. #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
  2763. #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
  2764. #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
  2765. #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
  2766. #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
  2767. #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
  2768. #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
  2769. #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
  2770. #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
  2771. #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
  2772. #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
  2773. #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
  2774. #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
  2775. #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
  2776. #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
  2777. #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
  2778. #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
  2779. #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
  2780. #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
  2781. #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
  2782. #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
  2783. #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
  2784. #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
  2785. #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
  2786. #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
  2787. #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
  2788. #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
  2789. #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
  2790. #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
  2791. #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
  2792. #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
  2793. #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
  2794. #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
  2795. #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
  2796. #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
  2797. #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
  2798. #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
  2799. #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
  2800. #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
  2801. #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
  2802. #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
  2803. #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
  2804. #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
  2805. #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
  2806. #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
  2807. #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
  2808. #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
  2809. #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
  2810. #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
  2811. #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
  2812. #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
  2813. #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
  2814. #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
  2815. #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
  2816. #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
  2817. #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
  2818. #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
  2819. #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
  2820. #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
  2821. #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
  2822. #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
  2823. #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
  2824. #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
  2825. #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
  2826. #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
  2827. #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
  2828. #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
  2829. #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
  2830. #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
  2831. #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
  2832. #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
  2833. #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
  2834. #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
  2835. #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
  2836. #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
  2837. #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
  2838. #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
  2839. #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
  2840. #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
  2841. #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
  2842. #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
  2843. #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
  2844. #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
  2845. #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
  2846. #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
  2847. #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
  2848. #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
  2849. #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
  2850. #if defined(STM32H7)
  2851. #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
  2852. #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
  2853. #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
  2854. #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
  2855. #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
  2856. #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
  2857. #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
  2858. #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
  2859. #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
  2860. #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
  2861. #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
  2862. #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
  2863. #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
  2864. #endif
  2865. #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
  2866. #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
  2867. #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
  2868. #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
  2869. #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
  2870. #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
  2871. #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
  2872. #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
  2873. #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
  2874. #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
  2875. #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
  2876. #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
  2877. #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
  2878. #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
  2879. #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
  2880. #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
  2881. #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
  2882. #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
  2883. #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
  2884. #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
  2885. #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
  2886. #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
  2887. #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
  2888. #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
  2889. #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
  2890. #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
  2891. #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
  2892. #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
  2893. #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
  2894. #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
  2895. #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
  2896. #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
  2897. #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
  2898. #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
  2899. #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
  2900. #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
  2901. #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
  2902. #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
  2903. #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
  2904. #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
  2905. #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
  2906. #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
  2907. #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
  2908. #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
  2909. #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
  2910. #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
  2911. #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
  2912. #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
  2913. #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
  2914. #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
  2915. #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
  2916. #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
  2917. #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
  2918. #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
  2919. #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
  2920. #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
  2921. #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
  2922. #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
  2923. #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
  2924. #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
  2925. #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
  2926. #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
  2927. #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
  2928. #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
  2929. #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
  2930. #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
  2931. #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
  2932. #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
  2933. #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
  2934. #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
  2935. #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
  2936. #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
  2937. #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
  2938. #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
  2939. #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
  2940. #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
  2941. #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
  2942. #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
  2943. #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
  2944. #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
  2945. #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
  2946. #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
  2947. #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
  2948. #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
  2949. #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
  2950. #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
  2951. #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
  2952. #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
  2953. #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
  2954. #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
  2955. #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
  2956. #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
  2957. #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
  2958. #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
  2959. #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
  2960. #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
  2961. #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
  2962. #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
  2963. #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
  2964. #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
  2965. #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
  2966. #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
  2967. #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
  2968. #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
  2969. #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
  2970. #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
  2971. #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
  2972. #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
  2973. #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
  2974. #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
  2975. #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
  2976. #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
  2977. #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
  2978. #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
  2979. #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
  2980. #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
  2981. #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
  2982. #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
  2983. #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
  2984. #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
  2985. #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
  2986. #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
  2987. #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
  2988. #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
  2989. #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
  2990. #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
  2991. #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
  2992. #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
  2993. #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
  2994. #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
  2995. #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
  2996. #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
  2997. #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
  2998. #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
  2999. #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
  3000. #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
  3001. #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
  3002. #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
  3003. #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
  3004. #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
  3005. #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
  3006. #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
  3007. #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
  3008. #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
  3009. #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
  3010. #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
  3011. #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
  3012. #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
  3013. #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
  3014. #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
  3015. #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
  3016. #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
  3017. #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
  3018. #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
  3019. #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
  3020. #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
  3021. #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
  3022. #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
  3023. #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
  3024. #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
  3025. #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
  3026. #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
  3027. #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
  3028. #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
  3029. #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
  3030. #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
  3031. #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
  3032. #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
  3033. #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
  3034. #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
  3035. #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
  3036. #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
  3037. #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
  3038. /* alias define maintained for legacy */
  3039. #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
  3040. #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
  3041. #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
  3042. #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
  3043. #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
  3044. #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
  3045. #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
  3046. #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
  3047. #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
  3048. #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
  3049. #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
  3050. #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
  3051. #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
  3052. #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
  3053. #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
  3054. #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
  3055. #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
  3056. #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
  3057. #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
  3058. #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
  3059. #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
  3060. #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
  3061. #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
  3062. #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
  3063. #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
  3064. #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
  3065. #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
  3066. #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
  3067. #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
  3068. #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
  3069. #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
  3070. #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
  3071. #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
  3072. #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
  3073. #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
  3074. #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
  3075. #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
  3076. #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
  3077. #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
  3078. #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
  3079. #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
  3080. #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
  3081. #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
  3082. #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
  3083. #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
  3084. #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
  3085. #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
  3086. #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
  3087. #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
  3088. #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
  3089. #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
  3090. #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
  3091. #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
  3092. #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
  3093. #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
  3094. #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
  3095. #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
  3096. #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
  3097. #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
  3098. #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
  3099. #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
  3100. #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
  3101. #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
  3102. #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
  3103. #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
  3104. #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
  3105. #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
  3106. #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
  3107. #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
  3108. #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
  3109. #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
  3110. #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
  3111. #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
  3112. #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
  3113. #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
  3114. #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
  3115. #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
  3116. #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
  3117. #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
  3118. #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
  3119. #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
  3120. #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
  3121. #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
  3122. #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
  3123. #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
  3124. #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
  3125. #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
  3126. #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
  3127. #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
  3128. #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
  3129. #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
  3130. #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
  3131. #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
  3132. #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
  3133. #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
  3134. #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
  3135. #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
  3136. #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
  3137. #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
  3138. #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
  3139. #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
  3140. #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
  3141. #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
  3142. #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
  3143. #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
  3144. #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
  3145. #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
  3146. #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
  3147. #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
  3148. #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
  3149. #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
  3150. #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
  3151. #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
  3152. #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
  3153. #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
  3154. #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
  3155. #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
  3156. #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
  3157. #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
  3158. #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
  3159. #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
  3160. #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
  3161. #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
  3162. #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
  3163. #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
  3164. #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
  3165. #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
  3166. #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
  3167. #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
  3168. #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
  3169. #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
  3170. #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
  3171. #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
  3172. #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
  3173. #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
  3174. #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
  3175. #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
  3176. #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
  3177. #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
  3178. #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
  3179. #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
  3180. #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
  3181. #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
  3182. #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
  3183. #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
  3184. #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
  3185. #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
  3186. #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
  3187. #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
  3188. #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
  3189. #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
  3190. #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
  3191. #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
  3192. #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
  3193. #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
  3194. #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
  3195. #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
  3196. #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
  3197. #if defined(STM32L1)
  3198. #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
  3199. #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
  3200. #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
  3201. #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
  3202. #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
  3203. #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
  3204. #endif /* STM32L1 */
  3205. #if defined(STM32F4)
  3206. #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
  3207. #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
  3208. #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
  3209. #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
  3210. #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
  3211. #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
  3212. #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
  3213. #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
  3214. #define Sdmmc1ClockSelection SdioClockSelection
  3215. #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
  3216. #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
  3217. #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
  3218. #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
  3219. #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
  3220. #endif
  3221. #if defined(STM32F7) || defined(STM32L4)
  3222. #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
  3223. #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
  3224. #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
  3225. #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
  3226. #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
  3227. #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
  3228. #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
  3229. #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
  3230. #define SdioClockSelection Sdmmc1ClockSelection
  3231. #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
  3232. #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
  3233. #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
  3234. #endif
  3235. #if defined(STM32F7)
  3236. #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
  3237. #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
  3238. #endif
  3239. #if defined(STM32H7)
  3240. #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
  3241. #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
  3242. #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
  3243. #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
  3244. #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
  3245. #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
  3246. #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
  3247. #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
  3248. #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
  3249. #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
  3250. #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
  3251. #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
  3252. #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
  3253. #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
  3254. #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
  3255. #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
  3256. #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
  3257. #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
  3258. #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
  3259. #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
  3260. #endif
  3261. #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
  3262. #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
  3263. #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
  3264. #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
  3265. #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
  3266. #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
  3267. #define IS_RCC_HCLK_DIV IS_RCC_PCLK
  3268. #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
  3269. #define RCC_IT_HSI14 RCC_IT_HSI14RDY
  3270. #define RCC_IT_CSSLSE RCC_IT_LSECSS
  3271. #define RCC_IT_CSSHSE RCC_IT_CSS
  3272. #define RCC_PLLMUL_3 RCC_PLL_MUL3
  3273. #define RCC_PLLMUL_4 RCC_PLL_MUL4
  3274. #define RCC_PLLMUL_6 RCC_PLL_MUL6
  3275. #define RCC_PLLMUL_8 RCC_PLL_MUL8
  3276. #define RCC_PLLMUL_12 RCC_PLL_MUL12
  3277. #define RCC_PLLMUL_16 RCC_PLL_MUL16
  3278. #define RCC_PLLMUL_24 RCC_PLL_MUL24
  3279. #define RCC_PLLMUL_32 RCC_PLL_MUL32
  3280. #define RCC_PLLMUL_48 RCC_PLL_MUL48
  3281. #define RCC_PLLDIV_2 RCC_PLL_DIV2
  3282. #define RCC_PLLDIV_3 RCC_PLL_DIV3
  3283. #define RCC_PLLDIV_4 RCC_PLL_DIV4
  3284. #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
  3285. #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
  3286. #define RCC_MCO_NODIV RCC_MCODIV_1
  3287. #define RCC_MCO_DIV1 RCC_MCODIV_1
  3288. #define RCC_MCO_DIV2 RCC_MCODIV_2
  3289. #define RCC_MCO_DIV4 RCC_MCODIV_4
  3290. #define RCC_MCO_DIV8 RCC_MCODIV_8
  3291. #define RCC_MCO_DIV16 RCC_MCODIV_16
  3292. #define RCC_MCO_DIV32 RCC_MCODIV_32
  3293. #define RCC_MCO_DIV64 RCC_MCODIV_64
  3294. #define RCC_MCO_DIV128 RCC_MCODIV_128
  3295. #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
  3296. #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
  3297. #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
  3298. #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
  3299. #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
  3300. #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
  3301. #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
  3302. #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
  3303. #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
  3304. #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
  3305. #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
  3306. #if defined(STM32U0)
  3307. #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
  3308. #endif
  3309. #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
  3310. defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
  3311. #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
  3312. #else
  3313. #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
  3314. #endif
  3315. #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
  3316. #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
  3317. #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
  3318. #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
  3319. #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
  3320. #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
  3321. #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
  3322. #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
  3323. #define HSION_BitNumber RCC_HSION_BIT_NUMBER
  3324. #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
  3325. #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
  3326. #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
  3327. #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
  3328. #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
  3329. #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
  3330. #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
  3331. #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
  3332. #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
  3333. #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
  3334. #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
  3335. #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
  3336. #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
  3337. #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
  3338. #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
  3339. #define LSION_BitNumber RCC_LSION_BIT_NUMBER
  3340. #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
  3341. #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
  3342. #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
  3343. #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
  3344. #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
  3345. #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
  3346. #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
  3347. #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
  3348. #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
  3349. #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
  3350. #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
  3351. #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
  3352. #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
  3353. #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
  3354. #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
  3355. #define CR_HSION_BB RCC_CR_HSION_BB
  3356. #define CR_CSSON_BB RCC_CR_CSSON_BB
  3357. #define CR_PLLON_BB RCC_CR_PLLON_BB
  3358. #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
  3359. #define CR_MSION_BB RCC_CR_MSION_BB
  3360. #define CSR_LSION_BB RCC_CSR_LSION_BB
  3361. #define CSR_LSEON_BB RCC_CSR_LSEON_BB
  3362. #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
  3363. #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
  3364. #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
  3365. #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
  3366. #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
  3367. #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
  3368. #define CR_HSEON_BB RCC_CR_HSEON_BB
  3369. #define CSR_RMVF_BB RCC_CSR_RMVF_BB
  3370. #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
  3371. #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
  3372. #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
  3373. #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
  3374. #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
  3375. #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
  3376. #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
  3377. #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
  3378. #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
  3379. #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
  3380. #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
  3381. #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
  3382. #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
  3383. #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
  3384. #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
  3385. #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
  3386. #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
  3387. #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
  3388. #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
  3389. #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
  3390. #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
  3391. #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
  3392. #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
  3393. #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
  3394. #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
  3395. #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
  3396. #define DfsdmClockSelection Dfsdm1ClockSelection
  3397. #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
  3398. #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
  3399. #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
  3400. #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
  3401. #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
  3402. #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
  3403. #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
  3404. #if !defined(STM32U0)
  3405. #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
  3406. #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
  3407. #endif
  3408. #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
  3409. #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
  3410. #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
  3411. #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
  3412. #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
  3413. #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
  3414. #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
  3415. #if defined(STM32U5)
  3416. #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
  3417. #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
  3418. #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
  3419. #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
  3420. #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
  3421. #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
  3422. #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
  3423. #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
  3424. #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
  3425. #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
  3426. #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
  3427. #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
  3428. #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
  3429. #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
  3430. #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
  3431. #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
  3432. #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
  3433. #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
  3434. #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
  3435. #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
  3436. #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
  3437. #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
  3438. #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
  3439. #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
  3440. #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
  3441. #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
  3442. #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
  3443. #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
  3444. #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
  3445. #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
  3446. #endif /* STM32U5 */
  3447. #if defined(STM32H5)
  3448. #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
  3449. #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
  3450. #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
  3451. #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
  3452. #define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
  3453. #define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
  3454. #define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
  3455. #define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
  3456. #define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
  3457. #define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
  3458. #define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
  3459. #define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
  3460. #define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
  3461. #define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
  3462. #define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
  3463. #define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
  3464. #define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
  3465. #define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
  3466. #define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
  3467. #define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
  3468. #define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
  3469. #define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
  3470. #define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
  3471. #define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
  3472. #define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
  3473. #define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
  3474. #define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
  3475. #define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
  3476. #define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
  3477. #define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
  3478. #define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
  3479. #define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
  3480. #define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
  3481. #define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
  3482. #define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
  3483. #define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
  3484. #define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
  3485. #define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
  3486. #define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
  3487. #define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
  3488. #define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
  3489. #define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
  3490. #define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
  3491. #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
  3492. #define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
  3493. #define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
  3494. #define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
  3495. #define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
  3496. #define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
  3497. #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
  3498. #define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
  3499. #define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
  3500. #define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
  3501. #define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
  3502. #define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
  3503. #define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
  3504. #define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
  3505. #define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
  3506. #define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
  3507. #define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
  3508. #define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
  3509. #define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
  3510. #define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
  3511. #define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
  3512. #define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
  3513. #define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
  3514. #define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
  3515. #define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
  3516. #define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
  3517. #define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
  3518. #endif /* STM32H5 */
  3519. /**
  3520. * @}
  3521. */
  3522. /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
  3523. * @{
  3524. */
  3525. #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
  3526. /**
  3527. * @}
  3528. */
  3529. /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
  3530. * @{
  3531. */
  3532. #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
  3533. defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
  3534. defined (STM32WBA) || defined (STM32H5) || \
  3535. defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
  3536. #else
  3537. #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
  3538. #endif
  3539. #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
  3540. #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
  3541. #if defined (STM32F1)
  3542. #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
  3543. #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
  3544. #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
  3545. #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
  3546. #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
  3547. #else
  3548. #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
  3549. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
  3550. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
  3551. #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
  3552. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
  3553. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
  3554. #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
  3555. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
  3556. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
  3557. #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
  3558. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
  3559. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
  3560. #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
  3561. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
  3562. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
  3563. #endif /* STM32F1 */
  3564. #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
  3565. defined (STM32H7) || \
  3566. defined (STM32L0) || defined (STM32L1) || \
  3567. defined (STM32WB)
  3568. #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
  3569. #endif
  3570. #define IS_ALARM IS_RTC_ALARM
  3571. #define IS_ALARM_MASK IS_RTC_ALARM_MASK
  3572. #define IS_TAMPER IS_RTC_TAMPER
  3573. #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
  3574. #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
  3575. #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
  3576. #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
  3577. #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
  3578. #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
  3579. #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
  3580. #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
  3581. #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
  3582. #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
  3583. #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
  3584. #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
  3585. #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
  3586. #if defined (STM32H5)
  3587. #define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
  3588. #define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
  3589. #endif /* STM32H5 */
  3590. /**
  3591. * @}
  3592. */
  3593. /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
  3594. * @{
  3595. */
  3596. #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
  3597. #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
  3598. #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
  3599. #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
  3600. #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
  3601. #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
  3602. #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
  3603. #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
  3604. #endif
  3605. #if defined(STM32F4) || defined(STM32F2)
  3606. #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
  3607. #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
  3608. #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
  3609. #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
  3610. #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
  3611. #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
  3612. #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
  3613. #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
  3614. #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
  3615. #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
  3616. #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
  3617. #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
  3618. #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
  3619. #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
  3620. #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
  3621. #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
  3622. #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
  3623. #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
  3624. #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
  3625. #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
  3626. /* alias CMSIS */
  3627. #define SDMMC1_IRQn SDIO_IRQn
  3628. #define SDMMC1_IRQHandler SDIO_IRQHandler
  3629. #endif
  3630. #if defined(STM32F7) || defined(STM32L4)
  3631. #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
  3632. #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
  3633. #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
  3634. #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
  3635. #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
  3636. #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
  3637. #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
  3638. #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
  3639. #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
  3640. #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
  3641. #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
  3642. #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
  3643. #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
  3644. #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
  3645. #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
  3646. #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
  3647. #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
  3648. #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
  3649. #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
  3650. #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
  3651. /* alias CMSIS for compatibilities */
  3652. #define SDIO_IRQn SDMMC1_IRQn
  3653. #define SDIO_IRQHandler SDMMC1_IRQHandler
  3654. #endif
  3655. #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
  3656. #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
  3657. #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
  3658. #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
  3659. #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
  3660. #endif
  3661. #if defined(STM32H7) || defined(STM32L5)
  3662. #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
  3663. #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
  3664. #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
  3665. #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
  3666. #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
  3667. #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
  3668. #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
  3669. #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
  3670. #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
  3671. #endif
  3672. /**
  3673. * @}
  3674. */
  3675. /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
  3676. * @{
  3677. */
  3678. #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
  3679. #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
  3680. #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
  3681. #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
  3682. #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
  3683. #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
  3684. #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
  3685. #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
  3686. #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
  3687. /**
  3688. * @}
  3689. */
  3690. /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
  3691. * @{
  3692. */
  3693. #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
  3694. #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
  3695. #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
  3696. #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
  3697. #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
  3698. #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
  3699. #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
  3700. #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
  3701. /**
  3702. * @}
  3703. */
  3704. /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
  3705. * @{
  3706. */
  3707. #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
  3708. #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
  3709. #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
  3710. /**
  3711. * @}
  3712. */
  3713. /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
  3714. * @{
  3715. */
  3716. #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
  3717. #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
  3718. #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
  3719. #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
  3720. #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
  3721. #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
  3722. #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
  3723. /**
  3724. * @}
  3725. */
  3726. /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
  3727. * @{
  3728. */
  3729. #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
  3730. #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
  3731. #define __USART_ENABLE __HAL_USART_ENABLE
  3732. #define __USART_DISABLE __HAL_USART_DISABLE
  3733. #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
  3734. #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
  3735. #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
  3736. #define USART_OVERSAMPLING_16 0x00000000U
  3737. #define USART_OVERSAMPLING_8 USART_CR1_OVER8
  3738. #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
  3739. ((__SAMPLING__) == USART_OVERSAMPLING_8))
  3740. #endif /* STM32F0 || STM32F3 || STM32F7 */
  3741. /**
  3742. * @}
  3743. */
  3744. /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
  3745. * @{
  3746. */
  3747. #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
  3748. #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
  3749. #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
  3750. #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
  3751. #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
  3752. #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
  3753. #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
  3754. #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
  3755. #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
  3756. #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
  3757. #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
  3758. #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
  3759. #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
  3760. #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
  3761. #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
  3762. #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
  3763. #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
  3764. #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
  3765. #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
  3766. #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
  3767. #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
  3768. #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
  3769. #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
  3770. #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
  3771. #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
  3772. #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
  3773. #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
  3774. #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
  3775. #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
  3776. #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
  3777. #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
  3778. #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
  3779. #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
  3780. #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
  3781. #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
  3782. #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
  3783. /**
  3784. * @}
  3785. */
  3786. /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
  3787. * @{
  3788. */
  3789. #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
  3790. #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
  3791. #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
  3792. #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
  3793. #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
  3794. #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
  3795. #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
  3796. #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
  3797. #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
  3798. #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
  3799. #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
  3800. #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
  3801. #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
  3802. #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
  3803. #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
  3804. #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
  3805. #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
  3806. #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
  3807. #define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
  3808. #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
  3809. /**
  3810. * @}
  3811. */
  3812. /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
  3813. * @{
  3814. */
  3815. #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
  3816. #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
  3817. #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
  3818. #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
  3819. #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
  3820. #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
  3821. #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
  3822. #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
  3823. #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
  3824. #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
  3825. /**
  3826. * @}
  3827. */
  3828. /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
  3829. * @{
  3830. */
  3831. #define __HAL_LTDC_LAYER LTDC_LAYER
  3832. #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
  3833. /**
  3834. * @}
  3835. */
  3836. /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
  3837. * @{
  3838. */
  3839. #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
  3840. #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
  3841. #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
  3842. #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
  3843. #define SAI_STREOMODE SAI_STEREOMODE
  3844. #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
  3845. #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
  3846. #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
  3847. #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
  3848. #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
  3849. #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
  3850. #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
  3851. #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
  3852. #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
  3853. /**
  3854. * @}
  3855. */
  3856. /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
  3857. * @{
  3858. */
  3859. #if defined(STM32H7)
  3860. #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
  3861. #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
  3862. #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
  3863. #endif
  3864. /**
  3865. * @}
  3866. */
  3867. /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
  3868. * @{
  3869. */
  3870. #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
  3871. #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
  3872. #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
  3873. #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
  3874. #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
  3875. #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
  3876. #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
  3877. #endif
  3878. /**
  3879. * @}
  3880. */
  3881. /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
  3882. * @{
  3883. */
  3884. #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
  3885. #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
  3886. #endif /* STM32L4 || STM32F4 || STM32F7 */
  3887. /**
  3888. * @}
  3889. */
  3890. /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
  3891. * @{
  3892. */
  3893. #if defined (STM32F7)
  3894. #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
  3895. #endif /* STM32F7 */
  3896. /**
  3897. * @}
  3898. */
  3899. /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
  3900. * @{
  3901. */
  3902. /**
  3903. * @}
  3904. */
  3905. #ifdef __cplusplus
  3906. }
  3907. #endif
  3908. #endif /* STM32_HAL_LEGACY */