stm32f0xx_hal_dma.c 26 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f0xx_hal_dma.c
  4. * @author MCD Application Team
  5. * @brief DMA HAL module driver.
  6. *
  7. * This file provides firmware functions to manage the following
  8. * functionalities of the Direct Memory Access (DMA) peripheral:
  9. * + Initialization and de-initialization functions
  10. * + IO operation functions
  11. * + Peripheral State and errors functions
  12. @verbatim
  13. ==============================================================================
  14. ##### How to use this driver #####
  15. ==============================================================================
  16. [..]
  17. (#) Enable and configure the peripheral to be connected to the DMA Channel
  18. (except for internal SRAM / FLASH memories: no initialization is
  19. necessary). Please refer to Reference manual for connection between peripherals
  20. and DMA requests .
  21. (#) For a given Channel, program the required configuration through the following parameters:
  22. Transfer Direction, Source and Destination data formats,
  23. Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
  24. using HAL_DMA_Init() function.
  25. (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
  26. detection.
  27. (#) Use HAL_DMA_Abort() function to abort the current transfer
  28. -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
  29. *** Polling mode IO operation ***
  30. =================================
  31. [..]
  32. (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
  33. address and destination address and the Length of data to be transferred
  34. (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
  35. case a fixed Timeout can be configured by User depending from his application.
  36. *** Interrupt mode IO operation ***
  37. ===================================
  38. [..]
  39. (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
  40. (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
  41. (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
  42. Source address and destination address and the Length of data to be transferred.
  43. In this case the DMA interrupt is configured
  44. (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
  45. (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
  46. add his own function by customization of function pointer XferCpltCallback and
  47. XferErrorCallback (i.e a member of DMA handle structure).
  48. *** DMA HAL driver macros list ***
  49. =============================================
  50. [..]
  51. Below the list of most used macros in DMA HAL driver.
  52. [..]
  53. (@) You can refer to the DMA HAL driver header file for more useful macros
  54. @endverbatim
  55. ******************************************************************************
  56. * @attention
  57. *
  58. * Copyright (c) 2016 STMicroelectronics.
  59. * All rights reserved.
  60. *
  61. * This software is licensed under terms that can be found in the LICENSE file in
  62. * the root directory of this software component.
  63. * If no LICENSE file comes with this software, it is provided AS-IS.
  64. *
  65. ******************************************************************************
  66. */
  67. /* Includes ------------------------------------------------------------------*/
  68. #include "stm32f0xx_hal.h"
  69. /** @addtogroup STM32F0xx_HAL_Driver
  70. * @{
  71. */
  72. /** @defgroup DMA DMA
  73. * @brief DMA HAL module driver
  74. * @{
  75. */
  76. #ifdef HAL_DMA_MODULE_ENABLED
  77. /* Private typedef -----------------------------------------------------------*/
  78. /* Private define ------------------------------------------------------------*/
  79. /* Private macro -------------------------------------------------------------*/
  80. /* Private variables ---------------------------------------------------------*/
  81. /* Private function prototypes -----------------------------------------------*/
  82. /** @defgroup DMA_Private_Functions DMA Private Functions
  83. * @{
  84. */
  85. static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  86. static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
  87. /**
  88. * @}
  89. */
  90. /* Exported functions ---------------------------------------------------------*/
  91. /** @defgroup DMA_Exported_Functions DMA Exported Functions
  92. * @{
  93. */
  94. /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
  95. * @brief Initialization and de-initialization functions
  96. *
  97. @verbatim
  98. ===============================================================================
  99. ##### Initialization and de-initialization functions #####
  100. ===============================================================================
  101. [..]
  102. This section provides functions allowing to initialize the DMA Channel source
  103. and destination addresses, incrementation and data sizes, transfer direction,
  104. circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
  105. [..]
  106. The HAL_DMA_Init() function follows the DMA configuration procedures as described in
  107. reference manual.
  108. @endverbatim
  109. * @{
  110. */
  111. /**
  112. * @brief Initialize the DMA according to the specified
  113. * parameters in the DMA_InitTypeDef and initialize the associated handle.
  114. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
  115. * the configuration information for the specified DMA Channel.
  116. * @retval HAL status
  117. */
  118. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
  119. {
  120. uint32_t tmp = 0U;
  121. /* Check the DMA handle allocation */
  122. if (NULL == hdma)
  123. {
  124. return HAL_ERROR;
  125. }
  126. /* Check the parameters */
  127. assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
  128. assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
  129. assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
  130. assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
  131. assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
  132. assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
  133. assert_param(IS_DMA_MODE(hdma->Init.Mode));
  134. assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
  135. /* Change DMA peripheral state */
  136. hdma->State = HAL_DMA_STATE_BUSY;
  137. /* Get the CR register value */
  138. tmp = hdma->Instance->CCR;
  139. /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
  140. tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
  141. DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
  142. DMA_CCR_DIR));
  143. /* Prepare the DMA Channel configuration */
  144. tmp |= hdma->Init.Direction |
  145. hdma->Init.PeriphInc | hdma->Init.MemInc |
  146. hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
  147. hdma->Init.Mode | hdma->Init.Priority;
  148. /* Write to DMA Channel CR register */
  149. hdma->Instance->CCR = tmp;
  150. /* Initialize DmaBaseAddress and ChannelIndex parameters used
  151. by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
  152. DMA_CalcBaseAndBitshift(hdma);
  153. /* Initialise the error code */
  154. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  155. /* Initialize the DMA state*/
  156. hdma->State = HAL_DMA_STATE_READY;
  157. /* Allocate lock resource and initialize it */
  158. hdma->Lock = HAL_UNLOCKED;
  159. return HAL_OK;
  160. }
  161. /**
  162. * @brief DeInitialize the DMA peripheral
  163. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  164. * the configuration information for the specified DMA Channel.
  165. * @retval HAL status
  166. */
  167. HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
  168. {
  169. /* Check the DMA handle allocation */
  170. if (NULL == hdma)
  171. {
  172. return HAL_ERROR;
  173. }
  174. /* Check the parameters */
  175. assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
  176. /* Disable the selected DMA Channelx */
  177. hdma->Instance->CCR &= ~DMA_CCR_EN;
  178. /* Reset DMA Channel control register */
  179. hdma->Instance->CCR = 0U;
  180. /* Reset DMA Channel Number of Data to Transfer register */
  181. hdma->Instance->CNDTR = 0U;
  182. /* Reset DMA Channel peripheral address register */
  183. hdma->Instance->CPAR = 0U;
  184. /* Reset DMA Channel memory address register */
  185. hdma->Instance->CMAR = 0U;
  186. /* Get DMA Base Address */
  187. DMA_CalcBaseAndBitshift(hdma);
  188. /* Clear all flags */
  189. hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
  190. /* Clean callbacks */
  191. hdma->XferCpltCallback = NULL;
  192. hdma->XferHalfCpltCallback = NULL;
  193. hdma->XferErrorCallback = NULL;
  194. hdma->XferAbortCallback = NULL;
  195. /* Reset the error code */
  196. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  197. /* Reset the DMA state */
  198. hdma->State = HAL_DMA_STATE_RESET;
  199. /* Release Lock */
  200. __HAL_UNLOCK(hdma);
  201. return HAL_OK;
  202. }
  203. /**
  204. * @}
  205. */
  206. /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
  207. * @brief I/O operation functions
  208. *
  209. @verbatim
  210. ===============================================================================
  211. ##### IO operation functions #####
  212. ===============================================================================
  213. [..] This section provides functions allowing to:
  214. (+) Configure the source, destination address and data length and Start DMA transfer
  215. (+) Configure the source, destination address and data length and
  216. Start DMA transfer with interrupt
  217. (+) Abort DMA transfer
  218. (+) Poll for transfer complete
  219. (+) Handle DMA interrupt request
  220. @endverbatim
  221. * @{
  222. */
  223. /**
  224. * @brief Start the DMA Transfer.
  225. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  226. * the configuration information for the specified DMA Channel.
  227. * @param SrcAddress The source memory Buffer address
  228. * @param DstAddress The destination memory Buffer address
  229. * @param DataLength The length of data to be transferred from source to destination
  230. * @retval HAL status
  231. */
  232. HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  233. {
  234. HAL_StatusTypeDef status = HAL_OK;
  235. /* Check the parameters */
  236. assert_param(IS_DMA_BUFFER_SIZE(DataLength));
  237. /* Process locked */
  238. __HAL_LOCK(hdma);
  239. if (HAL_DMA_STATE_READY == hdma->State)
  240. {
  241. /* Change DMA peripheral state */
  242. hdma->State = HAL_DMA_STATE_BUSY;
  243. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  244. /* Disable the peripheral */
  245. hdma->Instance->CCR &= ~DMA_CCR_EN;
  246. /* Configure the source, destination address and the data length */
  247. DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
  248. /* Enable the Peripheral */
  249. hdma->Instance->CCR |= DMA_CCR_EN;
  250. }
  251. else
  252. {
  253. /* Process Unlocked */
  254. __HAL_UNLOCK(hdma);
  255. /* Remain BUSY */
  256. status = HAL_BUSY;
  257. }
  258. return status;
  259. }
  260. /**
  261. * @brief Start the DMA Transfer with interrupt enabled.
  262. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  263. * the configuration information for the specified DMA Channel.
  264. * @param SrcAddress The source memory Buffer address
  265. * @param DstAddress The destination memory Buffer address
  266. * @param DataLength The length of data to be transferred from source to destination
  267. * @retval HAL status
  268. */
  269. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  270. {
  271. HAL_StatusTypeDef status = HAL_OK;
  272. /* Check the parameters */
  273. assert_param(IS_DMA_BUFFER_SIZE(DataLength));
  274. /* Process locked */
  275. __HAL_LOCK(hdma);
  276. if (HAL_DMA_STATE_READY == hdma->State)
  277. {
  278. /* Change DMA peripheral state */
  279. hdma->State = HAL_DMA_STATE_BUSY;
  280. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  281. /* Disable the peripheral */
  282. hdma->Instance->CCR &= ~DMA_CCR_EN;
  283. /* Configure the source, destination address and the data length */
  284. DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
  285. /* Enable the transfer complete, & transfer error interrupts */
  286. /* Half transfer interrupt is optional: enable it only if associated callback is available */
  287. if (NULL != hdma->XferHalfCpltCallback)
  288. {
  289. hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
  290. }
  291. else
  292. {
  293. hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
  294. hdma->Instance->CCR &= ~DMA_IT_HT;
  295. }
  296. /* Enable the Peripheral */
  297. hdma->Instance->CCR |= DMA_CCR_EN;
  298. }
  299. else
  300. {
  301. /* Process Unlocked */
  302. __HAL_UNLOCK(hdma);
  303. /* Remain BUSY */
  304. status = HAL_BUSY;
  305. }
  306. return status;
  307. }
  308. /**
  309. * @brief Abort the DMA Transfer.
  310. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  311. * the configuration information for the specified DMA Channel.
  312. * @retval HAL status
  313. */
  314. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
  315. {
  316. if (hdma->State != HAL_DMA_STATE_BUSY)
  317. {
  318. /* no transfer ongoing */
  319. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  320. /* Process Unlocked */
  321. __HAL_UNLOCK(hdma);
  322. return HAL_ERROR;
  323. }
  324. else
  325. {
  326. /* Disable DMA IT */
  327. hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
  328. /* Disable the channel */
  329. hdma->Instance->CCR &= ~DMA_CCR_EN;
  330. /* Clear all flags */
  331. hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
  332. }
  333. /* Change the DMA state*/
  334. hdma->State = HAL_DMA_STATE_READY;
  335. /* Process Unlocked */
  336. __HAL_UNLOCK(hdma);
  337. return HAL_OK;
  338. }
  339. /**
  340. * @brief Abort the DMA Transfer in Interrupt mode.
  341. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  342. * the configuration information for the specified DMA Stream.
  343. * @retval HAL status
  344. */
  345. HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
  346. {
  347. HAL_StatusTypeDef status = HAL_OK;
  348. if (HAL_DMA_STATE_BUSY != hdma->State)
  349. {
  350. /* no transfer ongoing */
  351. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  352. status = HAL_ERROR;
  353. }
  354. else
  355. {
  356. /* Disable DMA IT */
  357. hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
  358. /* Disable the channel */
  359. hdma->Instance->CCR &= ~DMA_CCR_EN;
  360. /* Clear all flags */
  361. hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
  362. /* Change the DMA state */
  363. hdma->State = HAL_DMA_STATE_READY;
  364. /* Process Unlocked */
  365. __HAL_UNLOCK(hdma);
  366. /* Call User Abort callback */
  367. if (hdma->XferAbortCallback != NULL)
  368. {
  369. hdma->XferAbortCallback(hdma);
  370. }
  371. }
  372. return status;
  373. }
  374. /**
  375. * @brief Polling for transfer complete.
  376. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  377. * the configuration information for the specified DMA Channel.
  378. * @param CompleteLevel Specifies the DMA level complete.
  379. * @param Timeout Timeout duration.
  380. * @retval HAL status
  381. */
  382. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
  383. {
  384. uint32_t temp;
  385. uint32_t tickstart = 0U;
  386. if (HAL_DMA_STATE_BUSY != hdma->State)
  387. {
  388. /* no transfer ongoing */
  389. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  390. __HAL_UNLOCK(hdma);
  391. return HAL_ERROR;
  392. }
  393. /* Polling mode not supported in circular mode */
  394. if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
  395. {
  396. hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
  397. return HAL_ERROR;
  398. }
  399. /* Get the level transfer complete flag */
  400. if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
  401. {
  402. /* Transfer Complete flag */
  403. temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
  404. }
  405. else
  406. {
  407. /* Half Transfer Complete flag */
  408. temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
  409. }
  410. /* Get tick */
  411. tickstart = HAL_GetTick();
  412. while (RESET == (hdma->DmaBaseAddress->ISR & temp))
  413. {
  414. if (RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
  415. {
  416. /* When a DMA transfer error occurs */
  417. /* A hardware clear of its EN bits is performed */
  418. /* Clear all flags */
  419. hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
  420. /* Update error code */
  421. hdma->ErrorCode = HAL_DMA_ERROR_TE;
  422. /* Change the DMA state */
  423. hdma->State = HAL_DMA_STATE_READY;
  424. /* Process Unlocked */
  425. __HAL_UNLOCK(hdma);
  426. return HAL_ERROR;
  427. }
  428. /* Check for the Timeout */
  429. if (Timeout != HAL_MAX_DELAY)
  430. {
  431. if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
  432. {
  433. /* Update error code */
  434. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  435. /* Change the DMA state */
  436. hdma->State = HAL_DMA_STATE_READY;
  437. /* Process Unlocked */
  438. __HAL_UNLOCK(hdma);
  439. return HAL_ERROR;
  440. }
  441. }
  442. }
  443. if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
  444. {
  445. /* Clear the transfer complete flag */
  446. hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
  447. /* The selected Channelx EN bit is cleared (DMA is disabled and
  448. all transfers are complete) */
  449. hdma->State = HAL_DMA_STATE_READY;
  450. }
  451. else
  452. {
  453. /* Clear the half transfer complete flag */
  454. hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
  455. }
  456. /* Process unlocked */
  457. __HAL_UNLOCK(hdma);
  458. return HAL_OK;
  459. }
  460. /**
  461. * @brief Handle DMA interrupt request.
  462. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  463. * the configuration information for the specified DMA Channel.
  464. * @retval None
  465. */
  466. void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
  467. {
  468. uint32_t flag_it = hdma->DmaBaseAddress->ISR;
  469. uint32_t source_it = hdma->Instance->CCR;
  470. /* Half Transfer Complete Interrupt management ******************************/
  471. if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
  472. {
  473. /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
  474. if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  475. {
  476. /* Disable the half transfer interrupt */
  477. hdma->Instance->CCR &= ~DMA_IT_HT;
  478. }
  479. /* Clear the half transfer complete flag */
  480. hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
  481. /* DMA peripheral state is not updated in Half Transfer */
  482. /* State is updated only in Transfer Complete case */
  483. if (hdma->XferHalfCpltCallback != NULL)
  484. {
  485. /* Half transfer callback */
  486. hdma->XferHalfCpltCallback(hdma);
  487. }
  488. }
  489. /* Transfer Complete Interrupt management ***********************************/
  490. else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
  491. {
  492. if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  493. {
  494. /* Disable the transfer complete & transfer error interrupts */
  495. /* if the DMA mode is not CIRCULAR */
  496. hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
  497. /* Change the DMA state */
  498. hdma->State = HAL_DMA_STATE_READY;
  499. }
  500. /* Clear the transfer complete flag */
  501. hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
  502. /* Process Unlocked */
  503. __HAL_UNLOCK(hdma);
  504. if (hdma->XferCpltCallback != NULL)
  505. {
  506. /* Transfer complete callback */
  507. hdma->XferCpltCallback(hdma);
  508. }
  509. }
  510. /* Transfer Error Interrupt management ***************************************/
  511. else if ((RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
  512. {
  513. /* When a DMA transfer error occurs */
  514. /* A hardware clear of its EN bits is performed */
  515. /* Then, disable all DMA interrupts */
  516. hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
  517. /* Clear all flags */
  518. hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
  519. /* Update error code */
  520. hdma->ErrorCode = HAL_DMA_ERROR_TE;
  521. /* Change the DMA state */
  522. hdma->State = HAL_DMA_STATE_READY;
  523. /* Process Unlocked */
  524. __HAL_UNLOCK(hdma);
  525. if (hdma->XferErrorCallback != NULL)
  526. {
  527. /* Transfer error callback */
  528. hdma->XferErrorCallback(hdma);
  529. }
  530. }
  531. }
  532. /**
  533. * @brief Register callbacks
  534. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  535. * the configuration information for the specified DMA Stream.
  536. * @param CallbackID User Callback identifier
  537. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
  538. * @param pCallback pointer to private callback function which has pointer to
  539. * a DMA_HandleTypeDef structure as parameter.
  540. * @retval HAL status
  541. */
  542. HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
  543. {
  544. HAL_StatusTypeDef status = HAL_OK;
  545. /* Process locked */
  546. __HAL_LOCK(hdma);
  547. if (HAL_DMA_STATE_READY == hdma->State)
  548. {
  549. switch (CallbackID)
  550. {
  551. case HAL_DMA_XFER_CPLT_CB_ID:
  552. hdma->XferCpltCallback = pCallback;
  553. break;
  554. case HAL_DMA_XFER_HALFCPLT_CB_ID:
  555. hdma->XferHalfCpltCallback = pCallback;
  556. break;
  557. case HAL_DMA_XFER_ERROR_CB_ID:
  558. hdma->XferErrorCallback = pCallback;
  559. break;
  560. case HAL_DMA_XFER_ABORT_CB_ID:
  561. hdma->XferAbortCallback = pCallback;
  562. break;
  563. default:
  564. status = HAL_ERROR;
  565. break;
  566. }
  567. }
  568. else
  569. {
  570. status = HAL_ERROR;
  571. }
  572. /* Release Lock */
  573. __HAL_UNLOCK(hdma);
  574. return status;
  575. }
  576. /**
  577. * @brief UnRegister callbacks
  578. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  579. * the configuration information for the specified DMA Stream.
  580. * @param CallbackID User Callback identifier
  581. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
  582. * @retval HAL status
  583. */
  584. HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
  585. {
  586. HAL_StatusTypeDef status = HAL_OK;
  587. /* Process locked */
  588. __HAL_LOCK(hdma);
  589. if (HAL_DMA_STATE_READY == hdma->State)
  590. {
  591. switch (CallbackID)
  592. {
  593. case HAL_DMA_XFER_CPLT_CB_ID:
  594. hdma->XferCpltCallback = NULL;
  595. break;
  596. case HAL_DMA_XFER_HALFCPLT_CB_ID:
  597. hdma->XferHalfCpltCallback = NULL;
  598. break;
  599. case HAL_DMA_XFER_ERROR_CB_ID:
  600. hdma->XferErrorCallback = NULL;
  601. break;
  602. case HAL_DMA_XFER_ABORT_CB_ID:
  603. hdma->XferAbortCallback = NULL;
  604. break;
  605. case HAL_DMA_XFER_ALL_CB_ID:
  606. hdma->XferCpltCallback = NULL;
  607. hdma->XferHalfCpltCallback = NULL;
  608. hdma->XferErrorCallback = NULL;
  609. hdma->XferAbortCallback = NULL;
  610. break;
  611. default:
  612. status = HAL_ERROR;
  613. break;
  614. }
  615. }
  616. else
  617. {
  618. status = HAL_ERROR;
  619. }
  620. /* Release Lock */
  621. __HAL_UNLOCK(hdma);
  622. return status;
  623. }
  624. /**
  625. * @}
  626. */
  627. /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
  628. * @brief Peripheral State functions
  629. *
  630. @verbatim
  631. ===============================================================================
  632. ##### State and Errors functions #####
  633. ===============================================================================
  634. [..]
  635. This subsection provides functions allowing to
  636. (+) Check the DMA state
  637. (+) Get error code
  638. @endverbatim
  639. * @{
  640. */
  641. /**
  642. * @brief Returns the DMA state.
  643. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  644. * the configuration information for the specified DMA Channel.
  645. * @retval HAL state
  646. */
  647. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
  648. {
  649. return hdma->State;
  650. }
  651. /**
  652. * @brief Return the DMA error code
  653. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  654. * the configuration information for the specified DMA Channel.
  655. * @retval DMA Error Code
  656. */
  657. uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
  658. {
  659. return hdma->ErrorCode;
  660. }
  661. /**
  662. * @}
  663. */
  664. /**
  665. * @}
  666. */
  667. /** @addtogroup DMA_Private_Functions
  668. * @{
  669. */
  670. /**
  671. * @brief Set the DMA Transfer parameters.
  672. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  673. * the configuration information for the specified DMA Channel.
  674. * @param SrcAddress The source memory Buffer address
  675. * @param DstAddress The destination memory Buffer address
  676. * @param DataLength The length of data to be transferred from source to destination
  677. * @retval HAL status
  678. */
  679. static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  680. {
  681. /* Clear all flags */
  682. hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
  683. /* Configure DMA Channel data length */
  684. hdma->Instance->CNDTR = DataLength;
  685. /* Memory to Peripheral */
  686. if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
  687. {
  688. /* Configure DMA Channel destination address */
  689. hdma->Instance->CPAR = DstAddress;
  690. /* Configure DMA Channel source address */
  691. hdma->Instance->CMAR = SrcAddress;
  692. }
  693. /* Peripheral to Memory */
  694. else
  695. {
  696. /* Configure DMA Channel source address */
  697. hdma->Instance->CPAR = SrcAddress;
  698. /* Configure DMA Channel destination address */
  699. hdma->Instance->CMAR = DstAddress;
  700. }
  701. }
  702. /**
  703. * @brief set the DMA base address and channel index depending on DMA instance
  704. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  705. * the configuration information for the specified DMA Stream.
  706. * @retval None
  707. */
  708. static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
  709. {
  710. #if defined (DMA2)
  711. /* calculation of the channel index */
  712. if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
  713. {
  714. /* DMA1 */
  715. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
  716. hdma->DmaBaseAddress = DMA1;
  717. }
  718. else
  719. {
  720. /* DMA2 */
  721. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
  722. hdma->DmaBaseAddress = DMA2;
  723. }
  724. #else
  725. /* calculation of the channel index */
  726. /* DMA1 */
  727. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
  728. hdma->DmaBaseAddress = DMA1;
  729. #endif
  730. }
  731. /**
  732. * @}
  733. */
  734. /**
  735. * @}
  736. */
  737. #endif /* HAL_DMA_MODULE_ENABLED */
  738. /**
  739. * @}
  740. */
  741. /**
  742. * @}
  743. */